Electrical Characteristics
MOTOROLA
MC68SC302 USER’S MANUAL
7-31
7.6.4.3 IDL TIMING SPECIFICATIONS.
NOTES:
1. The ratio EXTAL/L1CLK must be greater then 2.5/1.
2. High impedance is measured at the 30% and 70% of V
DD
points, with the line at V
DD
/2
through 10k in parallel with 130 pF.
3. Where P=1/EXTAL Thus, for a 20.48-MHz EXTAL rate, P=48.8 ns.
Table 7-15. IDL Timing Specifications
PARAMETER
CHARACTERISTICS
15.36MHZ
20.48MHZ
UNITS
MIN
MAX
MIN
MAX
t
idl1
t
idl2
t
idl3
L1CLK(idl clock) Frequency (see Note 1)
-
6
-
6
MHz
L1CLK width Low
60
-
60
-
ns
L1CLK width High (see Note 3)
p+10
-
p+10
-
ns
t
idl4
L1TxD,L1RQ,SDS1–SDS2 Rising/Falling
time
L1SYNC setup Time (to L1CLK Falling
Edge)
L1SYNC Hold Time (from L1CLK Falling
Edge)
-
17
-
17
ns
t
idl5
25
-
25
-
ns
t
idl6
40
-
40
-
ns
t
idl7
L1SYNC Inactive Before 4th L1CLK
0
-
0
-
ns
t
idl8
L1TxD Active Delay (from L1CLK Rising
Edge)
L1TxD to High Impedance (from L1CLK
Rising Edge) (see Note 2)
L1RxD Setup Time (to L1CLK Falling
Edge)
L1RxD Hold Time (from L1Clk Falling
Edge)
0
65
0
65
ns
t
idl9
0
50
0
50
ns
t
idl10
42
-
42
-
ns
t
idl11
42
-
42
-
ns
t
idl12
Time Between Successive IDL syncs
20
-
20
-
L1CLK
t
idl13
L1RQ Setup Time (to L1SYNC Falling
Edge)
L1GRNT Setup Time (to L1SYNC Falling
Edge)
L1GRNT Hold Time (from L1SYNC Falling
Edge)
SDS1–SDS2 Active Delay from L1CLK
Rising Edge
SDS1–SDS2 Inactive Delay from L1CLK
Falling Edge
1
-
1
-
L1CLK
t
idl14
42
-
42
-
ns
t
idl15
42
-
42
-
ns
t
idl16
10
65
10
65
ns
t
idl17
10
65
10
65
ns
