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| 型號(hào)： | MC68SC302 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 32-Bit Microprocessor(32位微處理器) |
| 中文描述： | 32位微處理器（32位微處理器） |
| 文件頁(yè)數(shù)： | 42/218頁(yè) |
| 文件大?。?/td> | 521K |
| 代理商： | MC68SC302 |
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Interrupt, Timer, and Power Control
3-2
MC68SC302 USER’S MANUAL
MOTOROLA
By masking all interrupt sources using the IMR, the user may implement a polling interrupt
servicing scheme for interrupts.
When an internal interrupt source from an on-chip peripheral has multiple interrupt events,
the user can individually mask these events by programming that peripheral's mask register.
In this case, when a masked event occurs, an interrupt request is not generated for the
associated interrupt source, and the corresponding bit in the IPR is not set. If the
corresponding bit in the IPR is already set, then masking the event in the peripheral mask
register causes the IPR bit to be cleared. To determine the cause of a pending interrupt
when an interrupt source has multiple interrupt events, the user interrupt service routine
must read the event register within that on-chip peripheral. By clearing all unmasked bits in
the event register, the IPR bit is also cleared.
3.1.3 Interrupt Handling Procedure
In order to process all interrupts by the host PC properly, the following procedure should be
followed for both edge and level triggered interrupts. When an interrupt is recognized by the
host CPU:
1. The host should clear the Mask All (MALL) bit in the IMR to mask all the interrupt
sources.
2. The host should read the IPR register and check which IPR bits are set, i.e., the source
that generated the interrupt. If more than one bit is set, then the host should process
the interrupts according to a user-defined priority.
3. The host should clear the IPR bit for the interrupt that was processed (by writing a “1”
to the IPR bit with all other bits set to “0” for the interrupt sources that do not have an
event register, or clearing the EVENT register bits in the same way).
4. The host should read the IPR register. If one or more bits are set, then it continues
from step #2 until all bits are cleared.
5. The host should clear the corresponding bit in the PC interrupt controller (PIC).
6. When all IPR bits are cleared, the host should set the MALL bit of the IMR and execute
a return from interrupt instruction immediately following the IMR update.
NOTE
If the return from interrupt is not executed immediately following
the IMR write, interrupt nesting may occur.
3.1.4 Wake Up On Interrupt
Wake up on interrupt is possible for the RI interrupt input only. When this functionality of the
pin IRQIN4/RI is selected by properly programming the Port A control registers, a rising
edge on the RI wakes up the SC302 from any of the low power modes. In PCMCIA mode,
the PC_STSCHG pin does the same if selected and enabled. In ISA mode, an interrupt is
generated to the PC after clock recovery.
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