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| 型號： | MC68MH360ZQ33LR2 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 90/158頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU QUICC 33MHZ 357-PBGA |
| 標(biāo)準(zhǔn)包裝： | 180 |
| 系列： | M683xx |
| 處理器類型： | M683xx 32-位 |
| 速度： | 33MHz |
| 電壓： | 5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 357-BBGA |
| 供應(yīng)商設(shè)備封裝： | 357-PBGA（25x25） |
| 包裝： | 帶卷 (TR) |
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Chapter 2. QMC Memory Organization
18
Rx_S_PTR
16
Rx time-slot assignment table pointer (default = SCC base + 20 in normal
mode)—This global QMC parameter denes the start value of the TSATRx
table, which must be present only once per SCC global area. Other SCCs may
access this location.
1A
TxPTR
16
TxPTR (initialize to SCC Base + 60)—This global parameter is a RISC variable
that points to the current transmitter time slot. The host must initialize it to the
starting location of TSATTx. The RISC processor increments this pointer
whenever it completes the processing of a transmitter time slot.
1C
C_MASK32
32
CRC constant (0xDEBB20E3)—Required to calculate 32-bit CRC-CCITT.
C_MASK32 is written by the host during QMC initialization. It is used for 32-bit
CRC-CCITT calculation if HDLC mode of operation is chosen for a selected
channel. (This is a programmable option. For each HDLC channel, one of two
CRCs can be chosen, as programmed in CHAMR.) For more information, see
Section 2.4.1, “Channel-Specic HDLC Parameters,” and Table 2-5. This entry
must have a correct value if at least one HDLC channel is used; otherwise, it
can be cleared (0).
20
TSATRx
32
Entries
x 16
Time slot assignment table Rx—Host-initialized, 16-bit-wide table with 32
entries that dene mapping of logical channels to time slots for the QMC
receiver. The QMC protocol looks at chunks of 8 bits regardless of whether they
come from one physical time slot of the TDM or whatever other combination of
bits the TSA transfers to the SCC. These 8 bits are referred to as a time slot in
the assignment table. It is recommended but not required to route all bits from
the TDM to the SCC and to do all enabling and masking in the time-slot
assignment table. See Figure 2-3.
60
TSATTx
32
Entries
x 16
Time slot assignment table Tx—Maps a specic logical channel to each
physical time slot. Time slot assignment table Tx is a host-initialized, 16-bit table
with 32 entries that dene the mapping of channels to time slots for the QMC
transmitter. The QMC protocol looks at chunks of 8 bits regardless if they go to
one physical time slot of the TDM or whatever other combination of bits are
transferred from the SCC to the TDM through the TSA. These 8 bits are referred
to as a time slot in the assignment table. It is recommended but not required to
route all bits from the TDM to the SCC and to do all enabling and masking in the
time slot assignment table. See Figure 2-3.
A0
C_MASK16
16
CRC constant (0xF0B8)—Required to calculate 16-bit CRC-CCITT. This
constant is written by the host during QMC initialization. It is used for 16-bit
CRC-CCITT calculation if HDLC mode of operation is chosen for a selected
channel. (This is a programmable option. For each HDLC channel, one of two
CRCs can be chosen, as programmed in CHAMR.) For more information, see
Section 2.4.1, “Channel-Specic HDLC Parameters,” and Table 2-5. This entry
must have a correct value if at least one HDLC channel is used; otherwise, it
can be cleared (0).
A4
TEMP_RBA
32
Temporary receive buffer address
A8
TEMP_CRC
32
Temporary cyclic redundancy check
Table 2-1. Global Multichannel Parameters (Continued)
Offset
to
SCC
Base
Name
Width
(Bits)
Description
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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