參數(shù)資料
型號: MC68MH360ZQ33LR2
廠商: Freescale Semiconductor
文件頁數(shù): 149/158頁
文件大?。?/td> 0K
描述: IC MPU QUICC 33MHZ 357-PBGA
標準包裝: 180
系列: M683xx
處理器類型: M683xx 32-位
速度: 33MHz
電壓: 5V
安裝類型: 表面貼裝
封裝/外殼: 357-BBGA
供應商設備封裝: 357-PBGA(25x25)
包裝: 帶卷 (TR)
QMC Supplement
5.3.4 MC68MH360 Congured for QMC and Ethernet
Certain difculties may arise when QMC and Ethernet are used together.
In a 25-MHz system, Ethernet can work together with 16 QMC channels. In this case, a
careful use of logical channels can free a 1-Kbyte space in the parameter area for up to 128
buffer descriptors. For more information, see Section 5.3.2, “Parameter RAM Usage for
QMC over Several SCCs.”
For 32-channel QMC operation coupled with Ethernet, a 33-MHz part is required. In
addition, Ethernet must operate on SCC1, and the QMC protocol must be divided over
SCC3 and SCC4 to use the combined FIFO size. This leaves SCC4’s parameter RAM page
unused as the largest single open space for the SCC1 Ethernet, resulting in 24 buffer
descriptors for transmission and reception in a single block. See Chapter 2, “QMC Memory
Organization,” for more information.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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