- 您現在的位置：買賣IC網 > PDF目錄3954 > MC68MH360ZQ33LR2 (Freescale Semiconductor)IC MPU QUICC 33MHZ 357-PBGA PDF資料下載
參數資料
| 型號： | MC68MH360ZQ33LR2 |
| 廠商： | Freescale Semiconductor |
| 文件頁數： | 129/158頁 |
| 文件大小： | 0K |
| 描述： | IC MPU QUICC 33MHZ 357-PBGA |
| 標準包裝： | 180 |
| 系列： | M683xx |
| 處理器類型： | M683xx 32-位 |
| 速度： | 33MHz |
| 電壓： | 5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 357-BBGA |
| 供應商設備封裝： | 357-PBGA（25x25） |
| 包裝： | 帶卷 (TR) |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁當前第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁
QMC Supplement
1—
—
2
W
Wrap (nal buffer descriptor in table)
0 This is not the last buffer descriptor in the RxBD table.
1 This is the last buffer descriptor in the RxBD table. After this buffer is used, the CPM receives
incoming data into the rst buffer descriptor in the table (the buffer descriptor pointed to by
RBASE). The number of RxBDs in this table is programmable and is determined only by the
wrap bit and by the space constraints of the dual-ported RAM.
3
I
Interrupt
0 The RXB bit will not be set after this buffer has been used, but RXF operation remains
unaffected.
1 The RXB bit (and/or the RXF bit in HDLC mode) of the interrupt table entry will be set when
this buffer has been used by the HDLC controller. These two bits may cause interrupts (if
enabled).
4
L
Last-in-frame (HDLC mode only)—The HDLC controller sets L when this buffer is the last in a
frame. This implies the receipt of a closing ag or reception of an error, in which case one or more
of the CD, OV, AB, and LG bits are set. The HDLC controller writes the number of frame octets to
the data length eld.
0 This buffer is not the last in a frame.
1 This buffer is the last in a frame.
5
F
First-in-frame—The controller sets this bit when this buffer is the rst in a frame.
0 The buffer is not the rst in a frame.
1 The buffer is the rst in a frame.
6
CM
Continuous Mode
0 Normal operation.
1 The empty bit is not cleared by the CPM after this buffer descriptor is closed, allowing the
associated data buffer to be overwritten automatically when the CPM next accesses this
buffer descriptor. The empty bit is not cleared if an error occurs during reception. The user
must terminate continuous mode by clearing this bit.
7—
—
8
UB
User bit—The CPM never touches, sets, or clears this user-dened bit. The user determines how
this bit is used. For example, it can be used to signal between higher level protocols whether a
buffer has been processed by the CPU.
9—
—
10
LG
Rx frame length violation (HDLC mode only)—A frame length greater than the maximum value
was received in this channel. Only the maximum-allowed number of bytes, MFLR rounded to the
nearest higher longword alignment, are written to the data buffer. This event is recognized as
soon as the MFLR value is exceeded when data is long-word-aligned. When data is not long-
word-aligned, this interrupt occurs when the SDMA writes 32 bits to memory. The worst-case
latency from MFLR violation until detected is 3-byte timings for this channel. When MFLR
violation is detected, the receiver is still receiving even though the data is discarded. The buffer is
closed when a ag is detected, and this is considered to be the closing ag for this buffer. At this
point, LG = 1 and an interrupt may be generated. The length eld for this buffer includes
everything between the opening ag and this last identied ag.
Table 5-1. Receive Buffer Descriptor (RxBD) Field Descriptions (Continued)
Field
Name
Description
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.
相關PDF資料 |
PDF描述 |
|---|---|
| IDT70V5378S100BG | IC SRAM 576KBIT 100MHZ 272BGA |
| MC7448HX1000LD | IC MPU RISC 32BIT 360-FCCBGA |
| MC68360ZQ25LR2 | IC MPU QUICC 25MHZ 357-PBGA |
| 346-012-520-804 | CARDEDGE 12POS DUAL .125 GREEN |
| 346-012-520-802 | CARDEDGE 12POS DUAL .125 GREEN |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MC68P11E1CFN2R2 | 制造商:Rochester Electronics LLC 功能描述:8BIT MCU 512RAM A/D EE - Bulk |
| MC68P11E1CFNE2R | 功能描述:8位微控制器 -MCU 8B MCU 512 BYTES RAM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| MC68P-3-2 | 制造商:PARKER 功能描述: |
| MC-68PLCC | 制造商:SPC Multicomp 功能描述:SOCKET PLCC 68 PIN THRU-HOLE 制造商:SPC Multicomp 功能描述:SOCKET, PLCC, 68 PIN, THRU-HOLE 制造商:PRIVATE LABEL 功能描述:PLCC SOCKET, 68POS, THROUGH HOLE, Connector Type:PLCC Socket, Series:-, No. of C 制造商:SPC Multicomp 功能描述:PLCC SOCKET, 68POS, THROUGH HOLE, Connector Type:PLCC Socket, Series:-, No. of Contacts:68, Pitch Spacing:1.27mm, Contact Termination:Through Hole Vertical, Contact Material:Phosphor Bronze, Contact Plating:Tin , RoHS Compliant: Yes |
| MC-68PLCC | 制造商:SPC Multicomp 功能描述:PLCC SOCKET 68POS THROUGH HOLE |
發(fā)布緊急采購，3分鐘左右您將得到回復。