參數資料
型號： MC68MH360ZQ33LR2
廠商： Freescale Semiconductor
文件頁數： 79/158頁
文件大?。?/td> 0K
描述： IC MPU QUICC 33MHZ 357-PBGA
標準包裝： 180
系列： M683xx
處理器類型： M683xx 32-位
速度： 33MHz
電壓： 5V
安裝類型： 表面貼裝
封裝/外殼： 357-BBGA
供應商設備封裝： 357-PBGA（25x25）
包裝： 帶卷 (TR)
Chapter 1.Overview
If a clock pulse is missing in a given frame N, the counter will fail to reach its end state
before the next sync pulse (N+1) arrives, causing that sync pulse to be ignored. When the
counter nally reaches its end state, it waits for the next sync pulse (N+2) before resetting.
Correct routing is thus resumed in frame (N+2). In the case of an extra clock pulse, the
counter reaches its end state too early and resumes synchronized routing upon detecting the
next sync pulse (N+1).
Synchronization pulse errors are similar to clock pulse errors. If the frame pulse comes too
late, this is similar to having missed a clock pulse in the last time slot. If the frame pulse is
too early, it is similar to having one additional clock pulse.
1.9 E1/T1 Frame Description
The primary rate ISDN connections offer a cost-effective, high-speed interface. The
physical connections in North America offer 24 connections over a T1 interface; in Europe
an E1 (or CEPT) connection gives 32 connections of 64 Kbps each with a time-division-
multiplexed architecture.
Time-division-multiplexing (TDM) allows several communication channels to share the
same physical media. The data stream of each channel is divided into a number of
subpackages. Each channel is then assigned a subdivision of the TDM line called a time
slot. This time slot is repeated over time in a regular pattern. A concatenation of the
channels’ subpackages comprises a frame. The frequency of frame repetition depends on
the particular communication interface. Two examples—the T1 line used in North America
and the E1 interface used in Europe illustrate TDM.
For both E1 and T1, the frames must be repeated at a frequency of 8 KHz, or every 125
s.
In many applications the required channel speed is 64 Kbps. For example, almost all voice
channels use 8-KHz sampling with 8-bit resolution. Each channel in a T1 or E1 interface
occupies 8 bits per time slot. The T1 interface multiplexes 24 channels, requiring 24 time
slots per frame. In addition to the channels’ bits, one more bit, for frame signaling and
synchronization, is added to create a frame totaling 193 bits. The resulting T1 physical
interface is thus 1.544 Mbps (8 KHz * 193 bits). The E1 frame consists of multiplexing
32 channels resulting in a speed of 2.048 Mbps (8 KHz * 256 bits). These two frames are
illustrated in Figure 1-8.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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