參數(shù)資料
型號： MC68MH360ZQ33LR2
廠商： Freescale Semiconductor
文件頁數(shù)： 19/158頁
文件大小： 0K
描述： IC MPU QUICC 33MHZ 357-PBGA
標準包裝： 180
系列： M683xx
處理器類型： M683xx 32-位
速度： 33MHz
電壓： 5V
安裝類型： 表面貼裝
封裝/外殼： 357-BBGA
供應(yīng)商設(shè)備封裝： 357-PBGA（25x25）
包裝： 帶卷 (TR)
Chapter 8.Performance
8.3 Bus Latency and Peak Load
Each time slot is 8 bits, but the QMC protocol transfers 32 bits of data whenever possible.
Thus, for each active channel operating within large frames, two 32-bit SDMA data
transfers (one for Tx and one for Rx) occur approximately every fourth TDM frame (every
500
s in CEPT/T1 interfaces). During buffer closing or opening, load will increase
approximately 3 to 4 times. Table 8-3 illustrates the bus activities involved when one QMC
channel switches from one Tx HDLC frame to the next.
Note: The table assumes the channel uses one time slot per TDM frame and that no PAD characters,
preceding ags or ag sharing is used.
In Table 8-3, the frame number refers to the 125-
s frame; the numbering is arbitrary but
sequential. The actions refer to the visible functions executed on the CPM. The number of
external bus cycles executed by the CPM represents the load on the bus.
The sequence in Table 8-3 starts when the last 32 bits are read from a buffer. One byte is
transferred over the TDM link per frame over the next four 125-
s frames. Then the CRC
is sent. In this case, it is a 16-bit CRC requiring two time slots over the next two frames.
The heavy load on the bus starts when the CPM must close the buffer in frame 8. At this
point the CPM needs three accesses to the bus to read and write to the interrupt table and
update the buffer descriptor’s status. In the following frame, the next buffer is opened
requiring three accesses to read the status and length, read the data pointer and read the data.
Table 8-3. QMC Actions in Tx Buffer Switch
Frame
Number
Actions
Number of
Bus Cycles
1
Read long word from buffer
(last in frame)
1
2
Send byte
0
3
Send byte
0
4
Send byte
0
5
Send last byte in frame
0
6
Send CRC
0
7
Send CRC
0
8
Send ag
Read interrupt table
Write interrupt table
Write BD
3
9
Send ag
Read next BD status/length
Read BD data pointer
Read data
3
10
Send rst byte of next frame
0
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.
相關(guān)PDF資料
PDF描述
IDT70V5378S100BG IC SRAM 576KBIT 100MHZ 272BGA
MC7448HX1000LD IC MPU RISC 32BIT 360-FCCBGA
MC68360ZQ25LR2 IC MPU QUICC 25MHZ 357-PBGA
346-012-520-804 CARDEDGE 12POS DUAL .125 GREEN
346-012-520-802 CARDEDGE 12POS DUAL .125 GREEN
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC68P11E1CFN2R2 制造商:Rochester Electronics LLC 功能描述:8BIT MCU 512RAM A/D EE - Bulk
MC68P11E1CFNE2R 功能描述:8位微控制器 -MCU 8B MCU 512 BYTES RAM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
MC68P-3-2 制造商:PARKER 功能描述:
MC-68PLCC 制造商:SPC Multicomp 功能描述:SOCKET PLCC 68 PIN THRU-HOLE 制造商:SPC Multicomp 功能描述:SOCKET, PLCC, 68 PIN, THRU-HOLE 制造商:PRIVATE LABEL 功能描述:PLCC SOCKET, 68POS, THROUGH HOLE, Connector Type:PLCC Socket, Series:-, No. of C 制造商:SPC Multicomp 功能描述:PLCC SOCKET, 68POS, THROUGH HOLE, Connector Type:PLCC Socket, Series:-, No. of Contacts:68, Pitch Spacing:1.27mm, Contact Termination:Through Hole Vertical, Contact Material:Phosphor Bronze, Contact Plating:Tin , RoHS Compliant: Yes
MC-68PLCC 制造商:SPC Multicomp 功能描述:PLCC SOCKET 68POS THROUGH HOLE
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*