參數(shù)資料
型號(hào)： MC68HC705C9ACP
廠商： Freescale Semiconductor
文件頁數(shù)： 92/118頁
文件大?。?/td> 0K
描述： IC MCU 2.1MHZ 16K OTP 40-DIP
標(biāo)準(zhǔn)包裝： 9
系列： HC05
核心處理器： HC05
芯體尺寸： 8-位
速度： 2.1MHz
連通性： SCI，SPI
外圍設(shè)備： POR，WDT
輸入/輸出數(shù)： 24
程序存儲(chǔ)器容量： 16KB（16K x 8）
程序存儲(chǔ)器類型： OTP
RAM 容量： 352 x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 40-DIP（0.600"，15.24mm）
包裝： 管件
SPI Registers
MC68HC05C9A Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
75
SPIE — Serial Peripheral Interrupt Enable Bit
This read/write bit enables SPI interrupts. Reset clears the SPIE bit.
1 = SPI interrupts enabled
0 = SPI interrupts disabled
SPE — Serial Peripheral System Enable Bit
This read/write bit enables the SPI. Reset clears the SPE bit.
1 = SPI system enabled
0 = SPI system disabled
DWOM — Port D Wire-OR Mode Option Bit
This read/write bit disables the high side driver transistors on port D outputs so that port D outputs
become open-drain drivers. DWOM affects all seven port D pins together. This option is only available
when configured as a C9A.
1 = Port D outputs act as open-drain outputs.
0 = Port D outputs are normal CMOS outputs.
MSTR — Master Mode Select Bit
This read/write bit selects master mode operation or slave mode operation. Reset clears the MSTR bit.
1 = Master mode
0 = Slave mode
CPOL — Clock Polarity Bit
When the clock polarity bit is cleared and data is not being transferred, a steady state low value is
produced at the SCK pin of the master device. Conversely, if this bit is set, the SCK pin will idle high.
This bit is also used in conjunction with the clock phase control bit to produce the desired clock-data
relationship between master and slave. See Figure 10-1.
CPHA — Clock Phase Bit
The clock phase bit, in conjunction with the CPOL bit, controls the clock-data relationship between
master and slave. The CPOL bit can be thought of as simply inserting an inverter in series with the
SCK line. The CPHA bit selects one of two fundamentally different clocking protocols. When
CPHA = 0, the shift clock is the OR of SCK with SS. As soon as SS goes low, the transaction begins
and the first edge on SCK invokes the first data sample. When CPHA=1, the SS pin may be thought
of as a simple output enable control. See Figure 10-1.
SPR1 and SPR0 — SPI Clock Rate Selects
These read/write bits select one of four master mode serial clock rates, as shown in Table 10-1. They
have no effect in the slave mode.
$000A
Bit 7
654321
Bit 0
Read:
SPIE
SPE
DWOM
(C9A)
MSTR
CPOL
CPHA
SPR1
SPR0
Write:
Reset:
000001
U
U = Undetermined
Figure 10-4. SPI Control Register (SPCR)
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MC68HC705C9ACPE 制造商:Freescale Semiconductor 功能描述:
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