參數(shù)資料
型號: MC68HC705C9ACP
廠商: Freescale Semiconductor
文件頁數(shù): 54/118頁
文件大?。?/td> 0K
描述: IC MCU 2.1MHZ 16K OTP 40-DIP
標(biāo)準(zhǔn)包裝: 9
系列: HC05
核心處理器: HC05
芯體尺寸: 8-位
速度: 2.1MHz
連通性: SCI,SPI
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 24
程序存儲器容量: 16KB(16K x 8)
程序存儲器類型: OTP
RAM 容量: 352 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 40-DIP(0.600",15.24mm)
包裝: 管件
Resets
MC68HC05C9A Advance Information Data Sheet, Rev. 4.1
40
Freescale Semiconductor
Figure 5-2. Power-On Reset and RESET
5.4 Computer Operating Properly (COP) Reset
This device includes a watchdog COP feature which guards against program run-away failures. A timeout
of the computer operating properly (COP) timer generates a COP reset. The COP watchdog is a software
error detection system that automatically times out and resets the MCU if not cleared periodically by a
program sequence.
This device includes two COP types, one for C12A compatibility and the other for C9A compatibility. When
configured as a C9A the COP can be enabled by user software by setting COPE in the C9A COP control
register (C9ACOPCR). When configured as a C12A, the COP is enabled prior to operation by
programming the C12COPE bit in the C12A mask option register (C12MOR). The function and control of
both COPs is detailed below.
RESET
OSC1
2
INTERNAL
CLOCK
1
INTERNAL
ADDRESS
BUS
1
V
DD
INTERNAL
DATA
BUS
1
t
RL
NEW
PCH
NEW
PCL
OP
CODe
OP
CODE
PCH
PCL
3
t
CYC
4064t
CYC
t
VDDR
DUMMY
3FFF
NEW
PC
NEW
PC
3FFE
NEW
PC
NEW
PC
3FFE
3FFF
3FFE
DUMMY
Notes:
1. Internal timing signal and bus information are not available externally.
2. OSC1 line is not meant to represent frequency. It is only meant to represent time.
3. The next rising edge of the internal processor clock following the rising edge of RESET initiates the reset sequence.
t
RL
3
RESET
(C9A)
(C12A)
4
4. RESET outputs VOL during 4064 power-on reset cycles when in C9A mode only.
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