參數(shù)資料
型號: MC68HC705C9ACP
廠商: Freescale Semiconductor
文件頁數(shù): 51/118頁
文件大?。?/td> 0K
描述: IC MCU 2.1MHZ 16K OTP 40-DIP
標準包裝: 9
系列: HC05
核心處理器: HC05
芯體尺寸: 8-位
速度: 2.1MHz
連通性: SCI,SPI
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 24
程序存儲器容量: 16KB(16K x 8)
程序存儲器類型: OTP
RAM 容量: 352 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 40-DIP(0.600",15.24mm)
包裝: 管件
Interrupts
MC68HC05C9A Advance Information Data Sheet, Rev. 4.1
38
Freescale Semiconductor
4.4 Timer Interrupt
Three different timer interrupt flags cause a timer interrupt whenever they are set and enabled. The
interrupt flags are in the timer status register (TSR), and the enable bits are in the timer control register
(TCR). Any of these interrupts will vector to the same interrupt service routine, located at the address
specified by the contents of memory locations $3FF8 and $3FF9.
4.5 SCI Interrupt
Five different SCI interrupt flags cause an SCI interrupt whenever they are set and enabled. The interrupt
flags are in the SCI status register (SCSR), and the enable bits are in the SCI control register 2 (SCCR2).
Any of these interrupts will vector to the same interrupt service routine, located at the address specified
by the contents of memory locations $3FF6 and $3FF7.
4.6 SPI Interrupt
Two different SPI interrupt flags cause an SPI interrupt whenever they are set and enabled. The interrupt
flags are in the SPI status register (SPSR), and the enable bits are in the SPI control register (SPCR).
Either of these interrupts will vector to the same interrupt service routine, located at the address specified
by the contents of memory locations $3FF4 and $3FF5.
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