參數(shù)資料
型號: MC68HC705C9ACP
廠商: Freescale Semiconductor
文件頁數(shù): 61/118頁
文件大小: 0K
描述: IC MCU 2.1MHZ 16K OTP 40-DIP
標(biāo)準(zhǔn)包裝: 9
系列: HC05
核心處理器: HC05
芯體尺寸: 8-位
速度: 2.1MHz
連通性: SCI,SPI
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 24
程序存儲器容量: 16KB(16K x 8)
程序存儲器類型: OTP
RAM 容量: 352 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 40-DIP(0.600",15.24mm)
包裝: 管件
MC68HC05C9A Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
47
Chapter 7
Input/Output (I/O) Ports
7.1 Introduction
This section briefly describes the 31 input/output (I/O) lines arranged as one 7-bit and three 8-bit ports.
All of these port pins are programmable as either inputs or outputs under software control of the data
direction registers.
NOTE
To avoid a glitch on the output pins, write data to the I/O port data register
before writing a one to the corresponding data direction register.
7.2 Port A
Port A is an 8-bit bidirectional port which does not share any of its pins with other subsystems. The port
A data register is at $0000 and the data direction register (DDR) is at $0004. The contents of the port A
data register are indeterminate at initial powerup and must be initialized by user software. Reset does not
affect the data registers, but clears the data direction registers, thereby returning the ports to inputs.
Writing a 1 to a DDR bit sets the corresponding port bit to output mode. A block diagram of the port logic
is shown in Figure 7-1.
Figure 7-1. Port A I/O Circuit
DATA DIRECTION
REGISTER BIT
LATCHED OUTPUT
DATA BIT
I/O
PIN
INPUT
REG
BIT
INPUT
I/O
OUTPUT
INTERNAL
HC05
CONNECTIONS
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