參數(shù)資料
型號(hào): MC68HC05C0B
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, 4 MHz, MICROCONTROLLER, PDIP42
封裝: SDIP-42
文件頁數(shù): 87/96頁
文件大?。?/td> 357K
代理商: MC68HC05C0B
Section 12: Serial Communications Interface
MOTOROLA
Page 79
MC68HC05C0 Specification Rev. 1.2
SCP1:0 - SCI Prescaler Bits
The SCP1 and SCP0 bits in the baud rate register are used to select a common prescaler
to increase the range of standard baud rates controlled by the SCR2:0 bits for the receiver
and the SCT2:0 bits for the transmitter. Reset clears these bits thereby causing the default
prescaler to be a divide by one. Refer to Table 12-3 for a list of highest transmission baud
rates with various crystal frequencies.
SCT2:0 - SCI Transmit Baud Rate Selection Bits
The SCT2, SCT1 and SCT0 bits in the baud rate register are used to select the baud rate
of the SCI transmitter. They further divide down the clock from the prescaler stage. See
Figure 12-14 : SCI Rate Generator Block Diagram. These bits are undefined after reset.
Refer to Table 12-4 for example baud rates from selected prescaler frequency outputs.
SCR2:0 - SCI Receiver Baud Rate Selection Bits
The SCR2, SCR1 and SCR0 bits in the baud rate register are used to select the baud rate
of the SCI receiver. They further divide down the clock from the prescaler stage. See
Figure 12-14 : SCI Rate Generator Block Diagram. These bits are undefined after reset.
Refer to Table 12-4 for example baud rates from selected prescaler frequency outputs.
Note that the final frequencies shown in Table 12-4 are baud rates. The receiver clock will
be 16 times higher to accommodate bit sampling.
Table 12-3: Prescaler Highest Baud Rate Frequency Output
* Refers to internal processor clock
SCP Bit
Clock*
Divided
By
Crystal Frequency MHz
1
0
16.0
8.0
4.9152
4.0
3.6864
00
1
250.0 kHz
125.0 kHz
76.80 kHz
62.50 kHz
57.60 kHz
01
3
83.333 kHz
41.666 kHz
25.60 kHz
20.833 kHz
19.20 kHz
10
4
62.50 kHz
31.25 kHz
19.20 kHz
15.625 kHz
14.40 kHz
11
13
19.20 kHz
9600 Hz
5.907 kHz
4800 Hz
4430 Hz
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