參數(shù)資料
型號(hào)： MC68HC05C0B
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, 4 MHz, MICROCONTROLLER, PDIP42
封裝： SDIP-42
文件頁數(shù)： 64/96頁
文件大?。?/td> 357K
代理商： MC68HC05C0B
MOTOROLA
Section 11: 16-Bit Timer
Page 58
MC68HC05C0 Specification Rev. 1.2
TOIE - Timer Overflow Interrupt Enable
1 = Interrupt enabled
0 = Interrupt disabled
OCM- Output Compare Mode
This bit allows Port B bit 0 to become the Timer Output Level (TCMP pin) regardless of the
state of the Port B bit 0 DDR bit. Note that the output compare functionality will still be active
when OCM is clear; however, TCMP will not be available externally.
1 = Port B bit 0 = TCMP
0 = Port B bit 0 = General Purpose I/O
ICM- Input Capture Mode
This bit allows Port B bit 1 to become the Timer Edge Input (TCAP pin) regardless of the
state of the Port B bit 1 DDR bit. TCAP has hysteresis to improve noise immunity. Note that
the input capture functionality will still be active when ICM is clear; however, the port will no
longer be TCAP. Therefore, care must be taken if port B bit 1 is a general purpose I/O since
it can still cause ICF to be set if the right transition occurs on the port pin (according to
IEDG). This implies that port B bit 1 can be made an output and manually toggled by
software to cause an input capture interrupt to occur if ICIE is set.
1 = Port B bit 1 = TCAP
0 = Port B bit 1 = General Purpose I/O
IEDG - Input Edge
Value of input edge determines which level transition on TCAP pin will trigger free-running
counter transfer to the input capture register.
1 = Positive edge
0 = Negative edge
Reset does not affect the IEDG bit (unaffected).
OLVL - Output Level
Value of output level is clocked into output level register by the next successful output
compare and will appear on the TCMP pin. The OCM should be set for the TCMP to be
visible externally.
1 = High output
0 = Low output
Bit 2 - Not used
Always reads zero
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