
Section 10: Multi-Function Timer
MOTOROLA
Page 49
MC68HC05C0 Specification Rev. 1.2
selection) stage goes active. A CPU interrupt request will be generated if RTIE is set.
Clearing the RTIF is done by writing a ’1’ to RTIFC. Writing to RTIF has no effect. Reset
clears RTIF.
10.2.3
TOFE - Timer Over Flow Enable
When this bit is set, a CPU interrupt request is generated when the TOF bit is set. When
this bit is clear, the TOF flag is prevented from generating an interrupt request. A reset
clears this bit.
10.2.4
RTIE - Real Time Interrupt Enable
When this bit is set, a CPU interrupt request is generated when the RTIF bit is set. When
this bit is clear, the RTIF flag is prevented from generating an interrupt request. A reset
clears this bit.
10.2.5
TOFC - Timer Over Flow Flag Clear
TOF is cleared by writing a logic 1 to TOFC. Writing a logic 0 to TOFC has no effect on
TOF. This bit always reads as logic 0.
10.2.6
RTIFC - Real Time Interrupt Flag Clear
RTIF is cleared by writing a logic 1 to RTIFC. Writing a logic 0 to RTIFC has no effect on
RTIF. This bit always reads as logic 0.
10.2.7
RT1:RT0 - Real Time Interrupt Rate Select
These two bits select one of four taps from the Real Time Interrupt circuit. Table 10-1 shows the available interrupt rates with a variety of oscillator frequencies. A reset sets
these two bits which selects the lowest periodic rate and gives the maximum time in which
to alter these bits if necessary. Care should be taken when altering RT0 and RT1 if the time-
out period is imminent or uncertain. If the selected tap is modified during a cycle in which
the counter is switching, an RTIF could be missed or an additional one could be generated.
To avoid problems, the COP should be cleared before changing RTI taps.
The encoding for these two bits is shown below.
Table 10-1: RTI Rates
RT1:RT0
16.0 MHz
8.0 MHz
00
8.192 ms
16.384 ms
01
16.384 ms
32.768 ms
10
32.768 ms
65.536 ms
11
RTI RATES AT fosc
8.192 ms
4.096 ms
FREQUENCY SPECIFIED: