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參數(shù)資料
| 型號： | MC68HC05C0B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 4 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | SDIP-42 |
| 文件頁數(shù)： | 59/96頁 |
| 文件大小： | 357K |
| 代理商： | MC68HC05C0B |
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Section 11: 16-Bit Timer
MOTOROLA
Page 53
MC68HC05C0 Specification Rev. 1.2
SECTION 11
16-BIT TIMER
11.1
INTRODUCTION
The timer consists of a 16-bit, software-programmable counter driven by a fixed divide-by-
four prescaler. This timer can be used for many purposes, including input waveform
measurements while simultaneously generating an output waveform. Pulse widths can
vary from several microseconds to many seconds. See Figure 11-1 below for a block
diagram of the 16-Bit Timer.
Because the timer has a 16-bit architecture, each specific functional segment is
represented by two registers. These registers contain the high and low byte of that
functional segment. Generally, accessing the low byte of a specific timer function allows full
control of that function; however, an access of the high byte inhibits that specific timer
function until the low byte is also accessed.
NOTE:
The I bit in the CCR should be set while manipulating both the high and
low byte register of a specific timer function to ensure that an interrupt
does not occur.
11.2
COUNTER
The key element in the programmable timer is a 16-bit, free-running counter or counter
register, preceded by a prescaler that divides the internal processor clock by four. The
prescaler gives the timer a resolution of 2.0 microseconds if the internal bus clock is 2.0
MHz. The counter is incremented during the low portion of the internal bus clock. Software
can read the counter at any time without affecting its value.
The double-byte, free-running counter can be read from either of two locations, $10-$11
(counter register) or $12-$13 (counter alternate register). A read from only the least
significant byte (LSB) of the free-running counter ($11, $13) receives the count value at the
time of the read. If a read of the free-running counter or counter alternate register first
addresses the most significant byte (MSB) ($10, $12), the LSB ($11, $13) is transferred to
a buffer. This buffer value remains fixed after the first MSB read, even if the user reads the
MSB several times. This buffer is accessed when reading the free-running counter or
counter alternate register LSB ($11 or $13) and, thus, completes a read sequence of the
total counter value. In reading either the free-running counter or counter alternate register,
if the MSB is read, the LSB must also be read to complete the sequence.
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