- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45216 > MC68302PV33C (FREESCALE SEMICONDUCTOR INC) 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144 PDF資料下載
參數(shù)資料
| 型號： | MC68302PV33C |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-144 |
| 文件頁數(shù)： | 76/128頁 |
| 文件大小： | 641K |
| 代理商： | MC68302PV33C |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁當前第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁
ETHERNET Controller
4-12
MC68EN302 REFERENCE MANUAL
MOTOROLA
PA_REJ—Physical address reject.
0 = Frames with physical addresses are accepted if there is a table match, either
perfect or hash.
1 = Frames with physical addresses are accepted if there is no perfect match. If a
physical address has a hash match but not a perfect match, the frame will be
accepted. This bit has no effect on frames with a multicast address.
PROM—Promiscuous mode.
0 = Frames are accepted only if they meet the hashing, perfect address match, or
MULT1–MULT0 criteria
1 = All frames are accepted regardless of address matching or settings of MULT1–
MULT0.
9–0—Reserved.
Should be written as zero by the host processor. These bits are always read as zero.
4.2 ETHERNET BUFFER DESCRIPTORS
The data for the Ethernet frames must reside in memory external to the MC68EN302 device
and is placed in one or more buffers. Buffer descriptors contain pointers to each buffer and
contain the current state of the buffer. The BDs are located inside the MC68EN302 in the
dual port Buffer Descriptor RAM so that the load on the processor bus is minimized.
Software “produces” buffers by allocating/initializing memory and initializing buffer
descriptors in the BDRAM. Setting the most significant bit (R for transmit and E for receive)
in the most significant word of the buffer descriptor initializes the buffer. MC68EN302 DMA
hardware constantly polls the BDs and processes the buffers after they have been
initialized. Processing in the case of transmit indicates that the data in the buffers has been
read into the MC68EN302 and transmitted out the Ethernet interface. Processing in the case
of receive indicates that data received from the Ethernet interface has been placed into data
buffers pointed to by the receive buffer descriptors. Once DMA is complete and the buffer
descriptor status bits have been written, the most signficant bit of the buffer descriptor is
cleared indicating that the buffer has been processed. Software may either poll the BDs or
may rely on the buffer/frame interrupts to detect when the buffers have been consumed.
The ETHER_EN signal operates as a reset to the BD/DMA logic. When ETHER_EN is
deasserted, the BD pointers are reset to point to the starting transmit and receive BDs. The
buffer descriptors are not initialized by hardware during reset. For proper operation, before
setting the ETHER_EN bit, initialize at least one transmit and receive buffer descriptor by
setting the most significant word of the descriptor to $0000 (this does not result in any
transmit or receive operation, but is considered to be initialization). Because the DMA polls
buffer descriptor memory to determine if the R/E bits in the next available BD are set
whenever ETHER_EN=1, initializing ‘n’ buffers, requires software to initialize n+1 buffer
descriptors, setting the most significant bit of the (n+1)th descriptor to 0.
相關PDF資料 |
PDF描述 |
|---|---|
| SPAK302PV16VC | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144 |
| SPAK302FC25C | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP132 |
| MC68EN360EM25 | 7 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP240 |
| MC68EN360FE33 | RISC MICROCONTROLLER, CQFP240 |
| MC68360RC25 | RISC MICROCONTROLLER, CPGA241 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MC68302RC16 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Integrated Multiprotocol Processor User’s Manual |
| MC68302RC16C | 功能描述:微處理器 - MPU 68K INTGR COM PROC DMA RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68302RC20 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Integrated Multiprotocol Processor User’s Manual |
| MC68302RC20C | 功能描述:微處理器 - MPU 68K INTGR COM PROC DMA RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68302RC25 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Integrated Multiprotocol Processor User’s Manual |
發(fā)布緊急采購，3分鐘左右您將得到回復。