參數(shù)資料
型號(hào)： MC68302PV33C
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝： 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-144
文件頁數(shù)： 71/128頁
文件大?。?/td> 641K
代理商： MC68302PV33C
ETHERNET Controller
4-8
MC68EN302 REFERENCE MANUAL
MOTOROLA
BSY—Busy Interrupt.
Indicates that the start of a frame was detected but a receive buffer was not available in
which to put the frame. If not corrected, this results in a FIFO overflow, which is indicated by
the OV bit in the receive buffer descriptor.
TXB—Transmit Buffer Interrupt.
Indicates that a transmit buffer descriptor with the I bit set in its status word has been
updated.
RXB—Receive Buffer Interrupt.
Indicates that a receive buffer descriptor with the I bit set in its status word has been
updated.
4.1.6 INTERRUPT MASK REGISTER (INTR_MASK)
The Interrupt Mask register provides control over which Ethernet controller events generate
an actual interrupt. The Interrupt Mask register is cleared on a hardware reset.
15–11—Reserved.
Must be written to zero by the host processor.
HBEEN—Heartbeat Error Interrupt Enable.
Enable interrupts when HBERR is set
BREN—Babbling Receiver Interrupt Enable.
Enable interrupts when BABR is set
BTEN—Babbling Transmitter Interrupt Enable.
Enable interrupts when BABT is set.
GRAEN—Graceful Stop Interrupt Enable.
Enable interrupts when GRA is set
BODEN—BackOff Done Enable.
Enable interrupts when BOD is set. This bit should always be cleared.
EBERREN—Ethernet Controller Bus Error Enable.
Enable interrupts when EBERR is set.
TFIEN—Transmit Frame Interrupt Enable.
Enable interrupts when TFINT is set.
RFIEN—Receive Frame Interrupt Enable.
Enable interrupts when RFINT is set.
15
14
13
12
11
10
98
7
6
5
43210
00000
HBEEN BREN BTEN
GRAEN
BODEN EBERREN TFIEN RFIEN BSYEN TBIEN RBIEN
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