參數(shù)資料
型號: MC68302PV33C
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝: 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-144
文件頁數(shù): 126/128頁
文件大?。?/td> 641K
代理商: MC68302PV33C
IEEE 1149.1 (JTAG) Test Access Port
7-12
MOTOROLA
Figure 7-10. General Arrangement for Bidirectional Pins
7.4 INSTRUCTION REGISTER
The MC68EN302 IEEE 1149.1 implementation includes the three mandatory public instruc-
tions (EXTEST, SAMPLE/PRELOAD, and BYPASS), and also supports the CLAMP instruc-
tion. One additional public instruction (HI-Z) provides the capability for disabling all device
output drivers. The MC68EN302 includes a 4-bit instruction register without parity. Data is
transferred from the shift register to the parallel outputs during the update-IR controller state.
The four bits used to decode the instructions are listed in Table 7-3.
The parallel output of the instruction register logic is reset to the equivalent to the BYPASS
instruction. During the capture-IR controller state, the parallel inputs to the instruction shift
register are loaded with 0001.
Table 7-3. Instruction Decoding
Code
IR[3]
IR[2]
IR[1]
IR[0]
Instruction
0000
EXTEST
0010
SAMPLE/PRELOAD
1111
BYPASS
1001
HI-Z
1100
CLAMP
ALL OTHER CASES
BYPASS
I/O
PIN
NOTE: More than one IO.Cell could be serially connected and controlled by a single IO.Ctl.
*
FROM LAST CELL
OUTPUT DATA
INPUT DATA
ENABLE FROM
DIRECTION CTL
SYSTEM LOGIC
IO CELL
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