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| 型號(hào)： | MC68302PV33C |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-144 |
| 文件頁(yè)數(shù)： | 108/128頁(yè) |
| 文件大?。?/td> | 641K |
| 代理商： | MC68302PV33C |
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MOTOROLA
MC68EN302 REFERENCE MANUAL
6-1
SECTION 6
APPLICATIONS
6.1 BRINGING THE MC68EN302 OUT OF RESET
The following paragraphs provide an example of how to bring the MC68EN302 out of reset
and initialize the Ethernet Controller to perform internal loopback of one frame. Bank 0 of
DRAM is used as packet memory.
1. Write the Base Address Register (BAR) with the desired starting point of the 302 core
4k-byte relocatable address space. Write the Module Bus Controller Base Address
Register (MOBAR) with the starting point of the 4k-byte relocatable address space for
the module bus controller, DRAM controller and Ethernet controller CSRS and
memory.
2. Write to the Option Register (OR) to include 256K bytes of space and so that the
DTACK field may be written to to change the number of wait states. Also note that to
access data in the program ROM, the CFC bits should be modified.
3. OR1 affects the RAM range, controls DTACK, and will also affect whether or not
function code comparisons are performed.
4. BR1 will set up the RAM address, enable the RAM, and set the function code
appropriately.
5. Switch from ROM location to dual-port RAM location to assure that the reset vector is
supplied by the ROM, but the exception vectors all come from the RAM. This switch is
performed by a short, dual-port RAM program which is summarized below, and is
explained in depth in Appendix D.2 of the MC68302 User’s Manual.
MOVE.W #$A001, (Address of BR1).L
MOVE.W #$C201, (Address or BR0).L
JMP
($Address in ROM).L
After the code is copied, then execute the following instruction, which will cause a
jump to dual port RAM
JMP
($Base Address).L
6. MBC - the MBC register controls bits for overall system level functionality of the
Module Bus Controller. This register must be initialized to assure smooth functionality
between the SIM module on the MC68EN302 and the SIM module on the internal 302
core. In the MBC register the module bus controller response to BCLR from the
internal 302 is controlled, as is the parity, function code for the Ethernet specific core,
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