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參數(shù)資料
| 型號： | MC68302PV33C |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-144 |
| 文件頁數(shù)： | 114/128頁 |
| 文件大?。?/td> | 641K |
| 代理商： | MC68302PV33C |
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MOTOROLA
MC68360 USER’S MANUAL
7-1
SECTION 7
IEEE 1149.1 (JTAG) TEST ACCESS PORT
The MC68EN302 provides a dedicated user-accessible test access port (TAP) that is fully
compatible with the
IEEE 1149.1 Standard Test Access Port and Boundary Scan Architec-
ture.
The TAP consists of five dedicated signal pins, a 16-state TAP controller, boundary scan
and instruction registers. A boundary scan register links I/O pins into a single shift register.
The test logic, implemented utilizing static logic design, is independent of the device system
logic. The MC68EN302 implementation provides the capability to:
1. Perform boundary scan operations to test circuit-board electrical continuity.
2. Bypass the MC68EN302 for a given circuit-board test by effectively reducing the
boundary scan register to a single cell.
3. Sample the MC68EN302 system pins during operation and transparently shift out the
result in the boundary scan register.
4. Disable the output drive to pins during circuit-board testing.
NOTE
Certain precautions must be observed to ensure that the IEEE
1149.-like test logic does not interfere with nontest operation.
See 7.6 Non-Scan Chain Operation for details.
In addition to the scan-test logic, the MC68EN302 contains a signal that can be used to
three-state all MC68EN302 output signals. This signal, called three-state (THREESTATE),
is sampled during system reset.
7.1 OVERVIEW
An overview of the MC68EN302 scan chain implementation is shown in Figure 7-1. The
MC68EN302 implementation includes a TAP controller, a 4-bit instruction register, and two
test registers (a 1-bit bypass register and a 163-bit boundary scan register). This implemen-
tation includes a dedicated TAP consisting of the following signals:
TCK—a test clock input to synchronize the test logic.
TMS—a test mode select input (with an internal pullup resistor) that is sampled on the
rising edge of TCK to sequence the TAP controller’s state machine.
TDI—a test data input (with an internal pullup resistor) that is sampled on the rising
edge of TCK.
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