參數(shù)資料
型號: MC56F8355VFG60
廠商: MOTOROLA INC
元件分類: 數(shù)字信號處理
英文描述: 4-BIT, 120 MHz, OTHER DSP, PQFP128
封裝: LQFP-128
文件頁數(shù): 75/152頁
文件大?。?/td> 2224K
代理商: MC56F8355VFG60
Introduction
56F8355 Technical Data
29
Preliminary
Part 3 On-Chip Clock Synthesis (OCCS)
3.1 Introduction
Refer to the OCCS chapter of the 56F8300 Peripheral User Manual for a full description of the
OCCS. The material contained here identifies the specific features of the OCCS design that apply
to the 56F8355 part. Figure 3-1 shows the specific OCCS block diagram to reference from the
OCCS chapter of the 56F8300 Peripheral User Manual.
Figure 3-1 OCCS Block Diagram
3.2 External Clock Operation
The 56F8355 system clock can be derived from an external crystal, ceramic resonator, or an
external system clock signal. To generate a reference frequency using the internal oscillator, a
reference crystal or ceramic resonator must be connected between the EXTAL and XTAL pins.
3.2.1
Crystal Oscillator
The internal oscillator is designed to interface with a parallel-resonant crystal resonator in the
frequency range specified for the external crystal in Table 10-15. A recommended crystal
oscillator circuit is shown in Figure 3-2. Follow the crystal supplier’s recommendations when
selecting a crystal, since crystal parameters determine the component values required to provide
MU
X
EXTAL
XTAL
F
E
ED
BAC
K
LCK
Prescaler CLK
Postscaler CLK
FOUT/2
Crystal
OSC
Loss of
Reference
Clock
Detector
Lock
Detector
ZSRC
Bus Interface & Control
FOUT
F
RE
F
PLLDB
PLLCOD
PLLCID
Bus
Interface
Loss of Reference
Clock Interrupt
SYS_CLK2
Source to SIM
MU
X
CLKMODE
÷2
Prescaler
÷ (1,2,4,8)
Postscaler
÷ (1,2,4,8)
MS
TR
_
O
S
C
PLL
x (1 to 128)
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