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參數(shù)資料
| 型號： | MC56F8355VFG60 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 4-BIT, 120 MHz, OTHER DSP, PQFP128 |
| 封裝： | LQFP-128 |
| 文件頁數(shù)： | 16/152頁 |
| 文件大?。?/td> | 2224K |
| 代理商： | MC56F8355VFG60 |
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112
56F8355 Technical Data
Preliminary
Part 7 Security Features
The 56F8355 offers security features intended to prevent unauthorized users from reading the
contents of the Flash Memory (FM) array. The 56F8355’s Flash security consists of several
hardware interlocks that block the means by which an unauthorized user could gain access to the
Flash array.
However, part of the security must lie with the user’s code. An extreme example would be user’s
code that dumps the contents of the internal program, as this code would defeat the purpose of
security. At the same time, the user may also wish to put a “backdoor” in his program. As an
example, the user downloads a security key through the SCI, allowing access to a programming
routine that updates parameters stored in another section of the Flash.
7.1 Operation with Security Enabled
Once the user has programmed the Flash with his application code, the 56F8355 can be secured by
programming the security bytes located in the FM configuration field, which occupies a portion of
the FM array. These non-volatile bytes will keep the part secured through reset and through
power-down of the device. Only two bytes within this field are used to enable or disable security.
Refer to the Flash Memory section in the 56F8300 Peripheral User Manual for the state of the
security bytes and the resulting state of security. When Flash security mode is enabled in
accordance with the method described in the Flash Memory module specification, the 56F8355
will disable the core EOnCE debug capabilities. Normal program execution is otherwise
unaffected.
7.2 Flash Access Blocking Mechanisms
The 56F8355 has several operating functional and test modes. Effective Flash security must
address operating mode selection and anticipate modes in which the on-chip Flash can be
compromised and read without explicit user permission. Methods to block these are outlined in the
next subsections.
7.2.1
Forced Operating Mode Selection
At boot time, the SIM determines in which functional modes the 56F8355 will operate. These are:
Unsecured Mode
Secure Mode (EOnCE disabled)
When Flash security is enabled as described in the Flash Memory module specification, the
56F8355 will disable the EOnCE debug interface.
7.2.2
Disabling EOnCE Access
On-chip Flash can be read by issuing commands across the EOnCE port, which is the debug
interface for the 56800E core. The TRST, TCLK, TMS, TDO, and TDI pins comprise a JTAG
interface onto which the EOnCE port functionality is mapped. When the 56F8355 boots, the
chip-level JTAG TAP (Test Access Port) is active and provides the chip’s boundary scan capability
and access to the ID register.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC56F8355VFGE | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16 BIT HYBRID CNTRLR RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| MC56F8356 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:56F8356 16-bit Hybrid Controller |
| MC56F8356MFV60 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC56F8356MFVE | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16 BIT HYBRID CONTROLLER RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| MC56F8356VFV60 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 60MHz 60MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
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