參數(shù)資料
型號: MC56F8355VFG60
廠商: MOTOROLA INC
元件分類: 數(shù)字信號處理
英文描述: 4-BIT, 120 MHz, OTHER DSP, PQFP128
封裝: LQFP-128
文件頁數(shù): 118/152頁
文件大小: 2224K
代理商: MC56F8355VFG60
68
56F8355 Technical Data
Preliminary
5.6 Register Descriptions
A register address is the sum of a base address and an address offset. The base address is defined
at the system level and the address offset is defined at the module level. The ITCN peripheral has
24 registers.
Table 5-3 ITCN Register Summary
(ITCN_BASE = $00F1A0)
Register
Acronym
Base Address +Register Name
Section Location
IPR0
$0
Interrupt Priority Register 0
IPR1
$1
Interrupt Priority Register 1
IPR2
$2
Interrupt Priority Register 2
IPR3
$3
Interrupt Priority Register 3
IPR4
$4
Interrupt Priority Register 4
IPR5
$5
Interrupt Priority Register 5
IPR6
$6
Interrupt Priority Register 6
IPR7
$7
Interrupt Priority Register 7
IPR8
$8
Interrupt Priority Register 8
IPR9
$9
Interrupt Priority Register 9
VBA
$A
Vector Base Address Register
FIM0
$B
Fast Interrupt 0 Match Register
FIVAL0
$C
Fast Interrupt 0 Vector Address Low Register
FIVAH0
$D
Fast Interrupt 0 Vector Address High Register
FIM1
$E
Fast Interrupt 1 Match Register
FIVAL1
$F
Fast Interrupt 1 Vector Address Low Register
FIVAH1
$10
Fast Interrupt 1 Vector Address High Register
IRQP0
$11
IRQ Pending Register 0
IRQP1
$12
IRQ Pending Register 1
IRQP2
$13
IRQ Pending Register 2
IRQP3
$14
IRQ Pending Register 3
IRQP4
$15
IRQ Pending Register 4
IRQP5
$16
IRQ Pending Register 5
Reserved
ICTL
$1 $1DD
Interrupt Control Register
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