參數(shù)資料
型號: MC56F8355VFG60
廠商: MOTOROLA INC
元件分類: 數(shù)字信號處理
英文描述: 4-BIT, 120 MHz, OTHER DSP, PQFP128
封裝: LQFP-128
文件頁數(shù): 15/152頁
文件大?。?/td> 2224K
代理商: MC56F8355VFG60
Resets
56F8355 Technical Data
111
Preliminary
The 56800E core contains both STOP and WAIT instructions. Both put the CPU to sleep. For
lowest power consumption in Stop mode, the PLL can be shut down. This must be done explicitly
before entering Stop mode, since there is no automatic mechanism for this. When the PLL is shut
down, the 56800E system clock must be set equal to the oscillator output.
Some applications require the 56800E STOP and WAIT instructions to be disabled. To disable
those instructions, write to the SIM control register (SIM_CONTROL), described in Section 6.5.1.
This procedure can be on either a permanent or temporary basis. Permanently assigned applications
last only until their next reset.
6.9 Resets
The SIM supports four sources of reset. The two asynchronous sources are the external RESET pin
and the Power-On Reset (POR). The two synchronous sources are the software reset, which is
generated within the SIM itself by writing to the SIM_CONTROL register, and the COP reset.
Reset begins with the assertion of any of the reset sources. Release of reset to various blocks is
sequenced to permit proper operation of the device. A POR reset is first extended for 221 clock
cycles to permit stabilization of the clock source, followed by a 32 clock window in which SIM
clocking is initiated. It is then followed by a 32 clock window in which peripherals are released to
implement Flash security, and, finally, followed by a 32 clock window in which the core is
initialized.
After completion of the described reset sequence, application code will begin
execution.
Resets may be asserted asynchronously, but are always released internally on a rising edge of the
system clock.
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