參數(shù)資料
型號: MC56F8347MPY60
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 16-BIT, 120 MHz, OTHER DSP, PQFP160
封裝: LQFP-160
文件頁數(shù): 91/172頁
文件大?。?/td> 2202K
代理商: MC56F8347MPY60
Signal Pins
56F8347 Technical Data, Rev. 5.0
Freescale Semiconductor
25
Preliminary
RD
52
Output
Tri-stated
Read Enable — RD is asserted during external memory read
cycles. When RD is asserted low, pins D0 - D15 become inputs
and an external device is enabled onto the data bus. When RD is
deasserted high, the external data is latched inside the device.
When RD is asserted, it qualifies the A0 - A16, PS, and DS pins.
RD can be connected directly to the OE pin of a static RAM or
ROM.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), RD is tri-stated when the external bus is inactive.
Most designs will want to change the DRV state to DRV = 1
instead of using the default setting.
To deactivate the internal pull-up resistor, set the CTRL bit in the
SIM_PUDR register.
WR
51
Output
Tri-stated
Write Enable — WR is asserted during external memory write
cycles. When WR is asserted low, pins D0 - D15 become
outputs and the device puts data on the bus. When WR is
deasserted high, the external data is latched inside the external
device. When WR is asserted, it qualifies the A0 - A16, PS, and
DS pins. WR can be connected directly to the WE pin of a static
RAM.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), WR is tri-stated when the external bus is inactive.
Most designs will want to change the DRV state to DRV = 1
instead of using the default setting.
To deactivate the internal pull-up resistor, set the CTRL bit in the
SIM_PUDR register.
Table 2-2 Signal and Package Information for the 160-Pin LQFP
Signal Name
Pin
No.
Type
State
During
Reset
Signal Description
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