參數(shù)資料
型號: MC56F8347MPY60
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 16-BIT, 120 MHz, OTHER DSP, PQFP160
封裝: LQFP-160
文件頁數(shù): 3/172頁
文件大?。?/td> 2202K
代理商: MC56F8347MPY60
56F8347 Technical Data, Rev. 5.0
100
Freescale Semiconductor
Preliminary
5.6.17.2
Fast Interrupt 1 Vector Address High (FIVAH1)—Bits 4–0
The upper five bits of the vector address are used for Fast Interrupt 1. This register is combined with
FIVAL1 to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register.
5.6.18
IRQ Pending 0 Register (IRQP0)
Figure 5-20 IRQ Pending 0 Register (IRQP0)
5.6.18.1
IRQ Pending (PENDING)—Bits 16–2
This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2
through 81.
0 = IRQ pending for this vector number
1 = No IRQ pending for this vector number
5.6.18.2
Reserved—Bit 0
This bit is reserved or not implemented. It is read as 1 and cannot be modified by writing.
5.6.19
IRQ Pending 1 Register (IRQP1)
Figure 5-21 IRQ Pending 1 Register (IRQP1)
5.6.19.1
IRQ Pending (PENDING)—Bits 32–17
This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2
through 81.
0 = IRQ pending for this vector number
1 = No IRQ pending for this vector number
5.6.20
IRQ Pending 2 Register (IRQP2)
Figure 5-22 IRQ Pending 2 Register (IRQP2)
Base + $11
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
PENDING [16:2]
1
Write
RESET
11111111
$Base + $12
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
PENDING [32:17]
Write
RESET
11111111
Base + $13
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
PENDING [48:33]
Write
RESET
11111111
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