
56F8347 Technical Data, Rev. 5.0
146
Freescale Semiconductor
Preliminary
Clock (SCK) low time
Master
Slave
tCL
24.1
25
—
ns
Data set-up time required for inputs
Master
Slave
tDS
20
0
—
ns
Data hold time required for inputs
Master
Slave
tDH
0
2
—
ns
Access time (time to data active from
high-impedance state)
Slave
tA
4.8
15
ns
Disable time (hold time to high-impedance state)
Slave
tD
3.7
15.2
ns
Data Valid for outputs
Master
Slave (after enable edge)
tDV
—
4.5
20.4
ns
Data invalid
Master
Slave
tDI
0
—
ns
Rise time
Master
Slave
tR
—
11.5
10.0
ns
Fall time
Master
Slave
tF
—
9.7
9.0
ns
1. Parameters listed are guaranteed by design.
Table 10-18 SPI Timing1 (Continued)
Characteristic
Symbol
Min
Max
Unit
See Figure