參數(shù)資料
型號: MC56F8347MPY60
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 16-BIT, 120 MHz, OTHER DSP, PQFP160
封裝: LQFP-160
文件頁數(shù): 20/172頁
文件大?。?/td> 2202K
代理商: MC56F8347MPY60
56F8347 Technical Data, Rev. 5.0
116
Freescale Semiconductor
Preliminary
6.5.8.1
Reserved—Bits 15–4
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.8.2
GPIOC3 (C3)—Bit 3
This bit selects the alternate function for GPIOC3.
0 = HOME1/TB3 (default - see “Switch Matrix Mode” bits of the Quad Decoder DECCR register in the
56F8300 Peripheral User’s Manual)
1 = SS1
6.5.8.3
GPIOC2 (C2)—Bit 2
This bit selects the alternate function for GPIOC2.
0 = INDEX1/TB2 (default)
1 = MISO1
6.5.8.4
GPIOC1 (C1)—Bit 1
This bit selects the alternate function for GPIOC1.
0 = PHASEB1/TB1 (default)
1 = MOSI1
6.5.8.5
GPIOC0 (C0)—Bit 0
This bit selects the alternate function for GPIOC0.
0 = PHASEA1/TB0 (default)
1 = SCLK1
6.5.9
Peripheral Clock Enable Register (SIM_PCE)
The Peripheral Clock Enable register is used to enable or disable clocks to the peripherals as a power
savings feature. The clocks can be individually controlled for each peripheral on the chip.
Figure 6-12 Peripheral Clock Enable Register (SIM_PCE)
6.5.9.1
External Memory Interface Enable (EMI)—Bit 15
Each bit controls clocks to the indicated peripheral.
1 = Clocks are enabled
0 = The clock is not provided to the peripheral (the peripheral is disabled)
Base + $C
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
EMI
ADCB ADCA
CAN
DEC1
DEC0
TMRD TMRC
TMRB
TMRA
SCI 1
SCI 0
SPI 1
SPI 0
PWMB
PWMA
Write
RESET
11
1
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