參數(shù)資料
型號: MC56F8347MPY60
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 16-BIT, 120 MHz, OTHER DSP, PQFP160
封裝: LQFP-160
文件頁數(shù): 107/172頁
文件大?。?/td> 2202K
代理商: MC56F8347MPY60
56F8347 Technical Data, Rev. 5.0
4
Freescale Semiconductor
Preliminary
Table of Contents
Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . . 5
1.1. 56F8347/56F8147 Features . . . . . . . . . . . . . 5
1.2. Device Description . . . . . . . . . . . . . . . . . . . . 7
1.3. Award-Winning Development Environment . 9
1.4. Architecture Block Diagram . . . . . . . . . . . . 10
1.5. Product Documentation . . . . . . . . . . . . . . . 14
1.6. Data Sheet Conventions . . . . . . . . . . . . . . 14
Part 2: Signal/Connection Descriptions . . . 15
2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2. Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . 18
Part 3: On-Chip Clock Synthesis (OCCS) . . 39
3.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.2. External Clock Operation . . . . . . . . . . . . . . 39
3.3. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Part 4: Memory Map . . . . . . . . . . . . . . . . . . . 41
4.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.2. Program Map . . . . . . . . . . . . . . . . . . . . . . . 42
4.3. Interrupt Vector Table . . . . . . . . . . . . . . . . . 43
4.4. Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.5. Flash Memory Map . . . . . . . . . . . . . . . . . . . 47
4.6. EOnCE Memory Map . . . . . . . . . . . . . . . . . 49
4.7. Peripheral Memory Mapped Registers . . . . 49
4.8. Factory Programmed Memory . . . . . . . . . . 75
Part 5: Interrupt Controller (ITCN) . . . . . . . . 76
5.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.3. Functional Description . . . . . . . . . . . . . . . . 76
5.4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . 78
5.5. Operating Modes . . . . . . . . . . . . . . . . . . . . 78
5.6. Register Descriptions . . . . . . . . . . . . . . . . . 79
5.7. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Part 6: System Integration Module (SIM) . 105
6.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.3. Operating Modes . . . . . . . . . . . . . . . . . . . 106
6.4. Operation Mode Register . . . . . . . . . . . . . 106
6.5. Register Descriptions . . . . . . . . . . . . . . . . 107
6.6. Clock Generation Overview . . . . . . . . . . . 120
6.7. Power-Down Modes Overview . . . . . . . . . 120
6.8. Stop and Wait Mode Disable Function . . . 121
6.9. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Part 7: Security Features . . . . . . . . . . . . . . 122
7.1. Operation with Security Enabled . . . . . . . 122
7.2. Flash Access Blocking Mechanisms . . . . 122
Part 8: General Purpose Input/Output
(GPIO) . . . . . . . . . . . . . . . . . . . . . . 125
8.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . 125
8.2. Memory Maps . . . . . . . . . . . . . . . . . . . . . . 125
8.3. Configuration . . . . . . . . . . . . . . . . . . . . . . . 125
Part 9: Joint Test Action Group (JTAG) . 130
9.1. JTAG Information . . . . . . . . . . . . . . . . . . . . 130
Part 10: Specifications . . . . . . . . . . . . . . . 130
10.1. General Characteristics . . . . . . . . . . . . . . 130
10.2. DC Electrical Characteristics . . . . . . . . . . 134
10.3. AC Electrical Characteristics . . . . . . . . . . 138
10.4. Flash Memory Characteristics . . . . . . . . . 138
10.5. External Clock Operation Timing . . . . . . . 139
10.6. Phase Locked Loop Timing . . . . . . . . . . . 139
10.7. Crystal Oscillator Timing . . . . . . . . . . . . . 140
10.8. External Memory Interface Timing . . . . . . 140
10.9. Reset, Stop, Wait, Mode Select, and
Interrupt Timing . . . . . . . . . . . . . . 143
10.10. Serial Peripheral Interface (SPI) Timing . 145
10.11. Quad Timer Timing . . . . . . . . . . . . . . . . 149
10.12. Quadrature Decoder Timing . . . . . . . . . . 149
10.13. Serial Communication Interface (SCI)
Timing . . . . . . . . . . . . . . . . . . . . . 150
10.14. Controller Area Network (CAN) Timing . 151
10.15. JTAG Timing . . . . . . . . . . . . . . . . . . . . . 151
10.16. Analog-to-Digital Converter (ADC)
Parameters . . . . . . . . . . . . . . . . . 153
10.17. Equivalent Circuit for ADC Inputs . . . . . . 156
10.18. Power Consumption . . . . . . . . . . . . . . . . 156
Part 11: Packaging . . . . . . . . . . . . . . . . . . 158
11.1. 56F8347 Package and Pin-Out
Information . . . . . . . . . . . . . . . . . . 158
11.2. 56F8147 Package and Pin-Out
Information . . . . . . . . . . . . . . . . . . 161
Part 12: Design Considerations . . . . . . . . 165
12.1. Thermal Design Considerations . . . . . . . . 165
12.2. Electrical Design Considerations . . . . . . . 166
12.3. Power Distribution and I/O Ring
Implementation . . . . . . . . . . . . . . 167
Part 13: Ordering Information . . . . . . . . . 168
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