參數(shù)資料
型號： MC56F8036VLF
廠商： Freescale Semiconductor
文件頁數(shù)： 96/164頁
文件大小： 0K
描述： IC DGTL SGNL CTLR 16BIT 48-LQFP
標(biāo)準(zhǔn)包裝： 1,250
系列： 56F8xxx
核心處理器： 56800E
芯體尺寸： 16-位
速度： 32MHz
連通性： CAN，I²C，SCI，SPI
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 39
程序存儲器容量： 64KB（32K x 16）
程序存儲器類型： 閃存
RAM 容量： 4K x 16
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 10x12b; D/A 2x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 48-LQFP
包裝： 托盤
產(chǎn)品目錄頁面： 734 (CN2011-ZH PDF)
Interrupt Vector Table
56F8036 Data Sheet, Rev. 6
Freescale Semiconductor
37
4.2 Interrupt Vector Table
Table 4-2 provides the 56F8036’s reset and interrupt priority structure, including on-chip peripherals. The
table is organized with higher-priority vectors at the top and lower-priority interrupts lower in the table.
As indicated, the priority of an interrupt can be assigned to different levels, allowing some control over
interrupt priorities. All level 3 interrupts will be serviced before level 2, and so on. For a selected priority
level, the lowest vector number has the highest priority.
The location of the vector table is determined by the Vector Base Address (VBA). Please see Section 5.6.8
for the reset value of the VBA.
By default, the chip reset address and COP reset address will correspond to vector 0 and 1 of the interrupt
vector table. In these instances, the first two locations in the vector table must contain branch or JMP
instructions. All other entries must contain JSR instructions.
Table 4-1 Chip Memory Configurations
On-Chip Memory
56F8036
Use Restrictions
Program Flash
(PFLASH)
32k x 16
or 64KB
Erase / Program via Flash interface unit and word writes to CDBW
Unified RAM (RAM)
4k x 16
or 8KB
Usable by both the Program and Data memory spaces
Table 4-2 Interrupt Vector Table Contents1
Peripheral
Vector
Number
Priority
Level
Vector Base
Address +
Interrupt Function
core
P:$00
Reserved for Reset Overlay2
core
P:$02
Reserved for COP Reset Overlay
core
2
3
P:$04
Illegal Instruction
core
3
P:$06
SW Interrupt 3
core
4
3
P:$08
HW Stack Overflow
core
5
3
P:$0A
Misaligned Long Word Access
core
6
1-3
P:$0C
EOnCE Step Counter
core
7
1-3
P:$0E
EOnCE Breakpoint Unit
core
8
1-3
P:$10
EOnCE Trace Buffer
core
9
1-3
P:$12
EOnCE Transmit Register Empty
core
10
1-3
P:$14
EOnCE Receive Register Full
core
11
2
P:$16
SW Interrupt 2
core
12
1
P:$18
SW Interrupt 1
core
13
0
P:$1A
SW Interrupt 0
14
Reserved
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC56F8036VLF 制造商:Freescale Semiconductor 功能描述:IC DSC 64KB 32MHZ 3.6V LQFP-48
MC56F8037 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers
MC56F8037EVM 功能描述:開發(fā)板和工具包 - 其他處理器 MC56F8037 EVAL BOARD RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓:
MC56F8037EVM 制造商:Freescale Semiconductor 功能描述:MC56F8037 EVALUATION BRD
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