參數(shù)資料
型號： MC56F8036VLF
廠商： Freescale Semiconductor
文件頁數(shù)： 147/164頁
文件大小： 0K
描述： IC DGTL SGNL CTLR 16BIT 48-LQFP
標(biāo)準(zhǔn)包裝： 1,250
系列： 56F8xxx
核心處理器： 56800E
芯體尺寸： 16-位
速度： 32MHz
連通性： CAN，I²C，SCI，SPI
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 39
程序存儲器容量： 64KB（32K x 16）
程序存儲器類型： 閃存
RAM 容量： 4K x 16
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 10x12b; D/A 2x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 48-LQFP
包裝： 托盤
產(chǎn)品目錄頁面： 734 (CN2011-ZH PDF)
Register Descriptions
56F8036 Data Sheet, Rev. 6
Freescale Semiconductor
83
6.3.1
SIM Control Register (SIM_CTRL)
Figure 6-2 SIM Control Register (SIM_CTRL)
6.3.1.1
Reserved—Bits 15–6
This bit field is reserved. Each bit must be set to 0.
6.3.1.2
OnCE Enable (ONCEEBL)—Bit 5
0 = OnCE clock to 56800E core enabled when core TAP is enabled
1 = OnCE clock to 56800E core is always enabled
Note:
Using default state “0” is recommended.
6.3.1.3
Software Reset (SWRST)—Bit 4
Writing 1 to this field will cause the device to reset
Read is 0
6.3.1.4
Stop Disable (STOP_DISABLE)—Bits 3–2
00 = Stop mode will be entered when the 56800E core executes a STOP instruction
01 = The 56800E STOP instruction will not cause entry into Stop mode
10 = Stop mode will be entered when the 56800E core executes a STOP instruction and the
STOP_DISABLE field is write-protected until the next reset
11 = The 56800E STOP instruction will not cause entry into Stop mode and the STOP_DISABLE field is
write-protected until the next reset
6.3.1.5
Wait Disable (WAIT_DISABLE)—Bits 1–0
00 = Wait mode will be entered when the 56800E core executes a WAIT instruction
01 = The 56800E WAIT instruction will not cause entry into Wait mode
10 = Wait mode will be entered when the 56800E core executes a WAIT instruction and the
WAIT_DISABLE field is write-protected until the next reset
11 = The 56800E WAIT instruction will not cause entry into Wait mode and the WAIT_DISABLE field is
write-protected until the next reset
6.3.2
SIM Reset Status Register (SIM_RSTAT)
This read-only register is updated upon any system reset and indicates the cause of the most recent reset.
It indicates whether the COP reset vector or regular reset vector (including Power-On Reset, External
Reset, Software Reset) in the vector table is used. This register is asynchronously reset during Power-On
Reset and subsequently is synchronously updated based on the precedence level of reset inputs. Only the
Base + $0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
ONCE
EBL
SW
RST
STOP_
DISABLE
WAIT_
DISABLE
Write
RESET
0
00
0
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