參數(shù)資料
型號(hào): MC56F8036VLF
廠商: Freescale Semiconductor
文件頁數(shù): 145/164頁
文件大小: 0K
描述: IC DGTL SGNL CTLR 16BIT 48-LQFP
標(biāo)準(zhǔn)包裝: 1,250
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 32MHz
連通性: CAN,I²C,SCI,SPI
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 39
程序存儲(chǔ)器容量: 64KB(32K x 16)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 4K x 16
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x12b; D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 48-LQFP
包裝: 托盤
產(chǎn)品目錄頁面: 734 (CN2011-ZH PDF)
Register Descriptions
56F8036 Data Sheet, Rev. 6
Freescale Semiconductor
81
6.3 Register Descriptions
A write to an address without an associated register is an NOP. A read from an address without an
associated register returns unknown data.
Table 6-1 SIM Registers (SIM_BASE = $00 F100)
Register
Acronym
Base Address +
Register Name
Section
Location
CTRL
$0
Control Register
RSTAT
$1
Reset Status Register
SWC0
$2
Software Control Register 0
SWC1
$3
Software Control Register 1
SWC2
$4
Software Control Register 2
SWC3
$5
Software Control Register 3
MSHID
$6
Most Significant Half of JTAG ID
LSHID
$7
Least Significant Half of JTAG ID
PWR
$8
Power Control Register
Reserved
CLKOUT
$A
CLKO Select Register
PCR
$B
Peripheral Clock Rate Register
PCE0
$C
Peripheral Clock Enable Register 0
PCE1
$D
Peripheral Clock Enable Register 0
SD0
$E
Stop Disable Register 0
SD1
$F
Stop Disable Register 1
IOSAHI
$10
I/O Short Address Location High Register
IOSALO
$11
I/O Short Address Location Low Register
PROT
$12
Protection Register
GPSA0
$13
GPIO Peripheral Select Register 0 for GPIOA
GPSA1
$14
GPIO Peripheral Select Register 1 for GPIOA
GPSB0
$15
GPIO Peripheral Select Register 0 for GPIOB
GPSB1
$16
GPIO Peripheral Select Register 1 for GPIOB
GPSCD
$17
GPIO Peripheral Select Register for GPIOC and GPIOD
IPS0
$18
Internal Peripheral Source Select Register 0 for PWM
IPSS1
$19
Internal Peripheral Source Select Register 1 for DACs
IPSS2
$1A
Internal Peripheral Source Select Register 2 for Quad Timer A
Reserved
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