參數(shù)資料
型號: MC56F8036VLF
廠商: Freescale Semiconductor
文件頁數(shù): 120/164頁
文件大?。?/td> 0K
描述: IC DGTL SGNL CTLR 16BIT 48-LQFP
標準包裝: 1,250
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 32MHz
連通性: CAN,I²C,SCI,SPI
外圍設備: POR,PWM,WDT
輸入/輸出數(shù): 39
程序存儲器容量: 64KB(32K x 16)
程序存儲器類型: 閃存
RAM 容量: 4K x 16
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉換器: A/D 10x12b; D/A 2x12b
振蕩器型: 內部
工作溫度: -40°C ~ 105°C
封裝/外殼: 48-LQFP
包裝: 托盤
產品目錄頁面: 734 (CN2011-ZH PDF)
Operating Modes
56F8036 Data Sheet, Rev. 6
Freescale Semiconductor
59
5.5 Operating Modes
The ITCN module design contains two major modes of operation:
Functional Mode
The ITCN is in this mode by default.
Wait and Stop Modes
During Wait and Stop modes, the system clocks and the 56800E core are turned off. The ITCN will signal
a pending IRQ to the System Integration Module (SIM) to restart the clocks and service the IRQ. An IRQ
can only wake up the core if the IRQ is enabled prior to entering the Wait or Stop mode.
5.6 Register Descriptions
A register address is the sum of a base address and an address offset. The base address is defined at the
system level and the address offset is defined at the module level.
Table 5-3 ITCN Register Summary
(ITCN_BASE = $00 F0E0)
Register
Acronym
Base Address +
Register Name
Section Location
IPR0
$0
Interrupt Priority Register 0
IPR1
$1
Interrupt Priority Register 1
IPR2
$2
Interrupt Priority Register 2
IPR3
$3
Interrupt Priority Register 3
IPR4
$4
Interrupt Priority Register 4
IPR5
$5
Interrupt Priority Register 5
IPR6
$6
Interrupt Priority Register 6
VBA
$7
Vector Base Address Register
FIM0
$8
Fast Interrupt Match 0 Register
FIVAL0
$9
Fast Interrupt 0 Vector Address Low Register
FIVAH0
$A
Fast Interrupt 0 Vector Address High 0 Register
FIM1
$B
Fast Interrupt Match 1 Register
FIVAL1
$C
Fast Interrupt 1 Vector Address Low Register
FIVAH1
$D
Fast Interrupt 1 Vector Address High Register
IRQP0
$E
IRQ Pending Register 0
IRQP1
$F
IRQ Pending Register 1
IRQP2
$10
IRQ Pending Register 2
IRQP3
$11
IRQ Pending Register 3
Reserved
ICTRL
$16
Interrupt Control Register
Reserved
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