參數(shù)資料
型號: MC56F8036VLF
廠商: Freescale Semiconductor
文件頁數(shù): 117/164頁
文件大?。?/td> 0K
描述: IC DGTL SGNL CTLR 16BIT 48-LQFP
標(biāo)準(zhǔn)包裝: 1,250
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 32MHz
連通性: CAN,I²C,SCI,SPI
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 39
程序存儲(chǔ)器容量: 64KB(32K x 16)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 4K x 16
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x12b; D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 48-LQFP
包裝: 托盤
產(chǎn)品目錄頁面: 734 (CN2011-ZH PDF)
56F8036 Data Sheet, Rev. 6
56
Freescale Semiconductor
Part 5 Interrupt Controller (ITCN)
5.1 Introduction
The Interrupt Controller (ITCN) module arbitrates between various interrupt requests (IRQs), signals to
the 56800E core when an interrupt of sufficient priority exists, and to what address to jump in order to
service this interrupt.
5.2 Features
The ITCN module design includes these distinctive features:
Programmable priority levels for each IRQ
Two programmable Fast Interrupts
Notification to SIM module to restart clocks out of Wait and Stop modes
Ability to drive initial address on the address bus after reset
For further information, see Table 4-2, Interrupt Vector Table Contents.
5.3 Functional Description
The Interrupt Controller is a slave on the IPBus. It contains registers that allow each of the 64 interrupt
sources to be set to one of four priority levels (excluding certain interrupts that are of fixed priority). Next,
all of the interrupt requests of a given level are priority encoded to determine the lowest numerical value
of the active interrupt requests for that level. Within a given priority level, number 0 is the highest priority
and number 63 is the lowest.
MSCAN_TXFG3
$33
Foreground Transmit Buffer 3
MSCAN_TXFG4
$34
Foreground Transmit Buffer 4
MSCAN_TXFG5
$35
Foreground Transmit Buffer 5
MSCAN_TXFG6
$36
Foreground Transmit Buffer 6
MSCAN_TXFG7
$37
Foreground Transmit Buffer 7
MSCAN_TXFG8
$38
Foreground Transmit Buffer 8
MSCAN_TXFG9
$39
Foreground Transmit Buffer 9
MSCAN_TXFG10
$3A
Foreground Transmit Buffer 10
MSCAN_TXFG11
$3B
Foreground Transmit Buffer 11
MSCAN_TXFG12
$3C
Foreground Transmit Buffer 12
MSCAN_TXFG13
$3D
Foreground Transmit Buffer 13
MSCAN_TXFG14
$3E
Foreground Transmit Buffer 14
MSCAN_TXFG15
$3F
Foreground Transmit Buffer 15
Reserved
Table 4-30 MSCAN Registers Address Map (Continued)
(MSCAN_BASE = $00 F800)
Register Acronym
Address Offset
Register Description
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