參數(shù)資料
型號： MC56F8036VLF
廠商： Freescale Semiconductor
文件頁數(shù)： 156/164頁
文件大小： 0K
描述： IC DGTL SGNL CTLR 16BIT 48-LQFP
標(biāo)準(zhǔn)包裝： 1,250
系列： 56F8xxx
核心處理器： 56800E
芯體尺寸： 16-位
速度： 32MHz
連通性： CAN，I²C，SCI，SPI
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 39
程序存儲器容量： 64KB（32K x 16）
程序存儲器類型： 閃存
RAM 容量： 4K x 16
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 10x12b; D/A 2x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 48-LQFP
包裝： 托盤
產(chǎn)品目錄頁面： 734 (CN2011-ZH PDF)
Register Descriptions
56F8036 Data Sheet, Rev. 6
Freescale Semiconductor
91
6.3.10.9
Quad Timer A, Channel 0 Clock Enable (TA0)—Bit 0
0 = The clock is not provided to the Timer A0 module (the Timer A0 module is disabled)
1 = The clock is enabled to the Timer A0 module
6.3.11
Stop Disable Register 0 (SD0)
By default, peripheral clocks are disabled during Stop mode in order to maximize power savings. This
register will allow an individual peripheral to operate in Stop mode. Since asserting an interrupt causes the
system to return to Run mode, this feature is provided so that selected peripherals can be left operating in
Stop mode for the purpose of generating a wake-up interrupt.
For power-conscious applications, it is recommended that only a minimum set of peripherals be
configured to remain operational during Stop mode.
Peripherals should be put in a non-operating (disabled) configuration prior to entering Stop mode unless
their corresponding Stop Disable control is set to 1. Refer to the 56F802X and 56F803XPeripheral
Reference Manual for further details. Reads and writes cannot be made to a module that has its clock
disabled.
Note:
The MSCAN module supports extended power management capabilities including Sleep,
Stop-in-Wait, and Disable modes. MSCAN clocks are selected by MSCAN control registers. For
details, refer to the 56F802X and 56F803XPeripheral Reference Manual.
Figure 6-12 Stop Disable Register 0 (SD0)
6.3.11.1
Comparator B Clock Stop Disable (CMPB_SD)—Bit 15
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
6.3.11.2
Comparator A Clock Stop Disable (CMPA_SD)—Bit 14
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
6.3.11.3
Digital-to-Analog Converter 1 Clock Stop Disable (DAC1_SD)—Bit 13
0 = The clock is disabled during Stop mode
1 = The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0
register
Base + $E
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
CMPB_
SD
CMPA_
SD
DAC1_
SD
DAC0_
SD
0
ADC_
SD
0
I2C_
SD
0
QSCI0_
SD
0
QSPI0_
SD
0
PWM_
SD
Write
RESET
0
00
0
000
0
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC56F8036VLF 制造商:Freescale Semiconductor 功能描述:IC DSC 64KB 32MHZ 3.6V LQFP-48
MC56F8037 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers
MC56F8037EVM 功能描述:開發(fā)板和工具包 - 其他處理器 MC56F8037 EVAL BOARD RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓:
MC56F8037EVM 制造商:Freescale Semiconductor 功能描述:MC56F8037 EVALUATION BRD
MC56F8037MLH 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16 BIT DSPHC RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
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