參數資料
型號: MC56F8014VFAE
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: 16-bit Digital Signal Controllers
中文描述: 16位數字信號控制器
文件頁數: 99/124頁
文件大小: 1878K
代理商: MC56F8014VFAE
External Clock Operation Timing
56F8014 Technical Data, Rev. 3
Freescale Semiconductor
Preliminary
99
10.5 External Clock Operation Timing
Figure 10-4 External Clock Timing
10.6 Phase Locked Loop Timing
Table 10-10 External Clock Operation Timing Requirements
1
1. Parameters listed are guaranteed by design.
2. See
Figure 10-4
for details on using the recommended connection of an external clock driver.
3. The high or low pulse width must be no smaller than 6.25ns or the chip may not function.
4. External clock input rise time is measured from 10% to 90%.
5. External clock input fall time is measured from 90% to 10%.
Characteristic
Symbol
Min
Typ
Max
Unit
Frequency of operation (external clock driver)
2
f
osc
4
8
8
MHz
Clock Pulse Width
3
t
PW
6.25
ns
External Clock Input Rise Time
4
t
rise
3
ns
External Clock Input Fall Time
5
t
fall
3
ns
Table 10-11 PLL Timing
Characteristic
Symbol
Min
Typ
Max
Unit
Internal reference relaxation oscillator frequency for
the PLL
f
rosc
8
MHz
PLL output frequency
1
(24 x reference frequency)
1. The core system clock will operate at 1/6 of the PLL output frequency.
2. This is the time required after the PLL is enabled to ensure reliable operation.
f
op
192
MHz
PLL lock time
2
t
lock
.1
1
ms
Cycle to cycle jitter
t
jitterpll
350
ps
External
Clock
V
IH
V
IL
Note: The midpoint is V
IL
+ (V
IH
– V
IL
)/2.
90%
50%
10%
90%
50%
10%
t
PW
t
PW
t
fall
t
rise
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