參數(shù)資料
型號: MC56F8014VFAE
廠商: 飛思卡爾半導體(中國)有限公司
英文描述: 16-bit Digital Signal Controllers
中文描述: 16位數(shù)字信號控制器
文件頁數(shù): 58/124頁
文件大?。?/td> 1878K
代理商: MC56F8014VFAE
56F8014 Technical Data, Rev. 3
58
Freescale Semiconductor
Preliminary
5.6.12.2 Fast Interrupt 1 Vector Address High (FIVAH1)—Bits 4–0
The upper five bits of the vector address are used for Fast Interrupt 1. This register is combined with
FIVAL1
to form the 21-bit vector address for Fast Interrupt 1 defined in the FIM1 register.
5.6.13
IRQ Pending Register 0 (IRQP0)
Figure 5-15 IRQ Pending Register 0 (IRQP0)
5.6.13.1 IRQ Pending (PENDING)—Bits 15–1
This register combines with IRQP1 and IRQP2 to represent the pending IRQs for interrupt vector numbers
2 through 45.
0 = IRQ pending for this vector number
1 = No IRQ pending for this vector number
5.6.13.2 Reserved—Bit 0
This bit is reserved or not implemented. It is read as 1 and cannot be modified by writing.
5.6.14
IRQ Pending Register 1 (IRQP1)
Figure 5-16 IRQ Pending Register 1 (IRQP1)
5.6.14.1 IRQ Pending (PENDING)—Bits 32–17
This register combines with IRQP0 and IRQP2 to represent the pending IRQs for interrupt vector numbers
2 through 45.
0 = IRQ pending for this vector number
1 = No IRQ pending for this vector number
5.6.15
IRQ Pending Register 2 (IRQP2)
Figure 5-17 IRQ Pending Register 2 (IRQP2)
Base + $C
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
Write
RESET
PENDING[16:2]
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Base + $D
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
Write
RESET
PENDING[32:17]
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Base + $E
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
Write
RESET
1
1
1
PENDING[45:33]
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
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