參數(shù)資料
型號: MC56F8014VFAE
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: 16-bit Digital Signal Controllers
中文描述: 16位數(shù)字信號控制器
文件頁數(shù): 68/124頁
文件大小: 1878K
代理商: MC56F8014VFAE
56F8014 Technical Data, Rev. 3
68
Freescale Semiconductor
Preliminary
Figure 6-5 Most Significant Half of JTAG ID (SIM_MSHID)
6.3.5
This read-only register displays the least significant half of the JTAG ID for the chip. This register reads
$401D.
Least Significant Half of JTAG ID (SIM_LSHID)
Figure 6-6 Least Significant Half of JTAG ID (SIM_LSHID)
6.3.6
This register controls the Standby mode of the large regulator. The large regulator derives the core digital
logic power supply from the IO power supply. In some circumstances, the large regulator may be put in a
reduced-power Standby mode without interfering with part operation. Refer to the overview of
power-down modes and the overview of clock generation for more information on the use of large
regulator standby.
SIM Power Control Register (SIM_PWR)
Figure 6-7 SIM Power Control Register (SIM_PWR)
6.3.6.1
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
Reserved—Bits 15–2
6.3.6.2
This bit controls the pull-up resistors on the IRQA pin.
Large Regulator Standby Mode[1:0] (LRSTDBY)—Bits 1–0
00 = Large regulator is in Normal mode
01 = Large regulator is in Standby (reduced-power) mode
10 = Large regulator is in Normal mode and the LRSTDBY field is write-protected until the next reset
11 = Large regulator is in Standby mode and the LRSTDBY field is write-protected until the next reset
Base + $6
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
Write
RESET
0
0
0
0
0
0
0
1
1
1
1
1
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
1
0
Base + $7
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
Write
RESET
0
1
0
0
0
0
0
0
0
0
0
1
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
1
1
1
0
1
Base + $8
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LRSTDBY
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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