參數(shù)資料
型號： MC56F8014VFAE
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述： 16-bit Digital Signal Controllers
中文描述： 16位數(shù)字信號控制器
文件頁數(shù)： 111/124頁
文件大?。?/td> 1878K
代理商： MC56F8014VFAE
Power Consumption
56F8014 Technical Data, Rev. 3
Freescale Semiconductor
Preliminary
111
1.
2.
3.
4.
Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling; 1.8pF
Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing; 2.04pF
Equivalent resistance for the channel select mux; 100 ohms
Sampling capacitor at the sample and hold circuit. Capacitor C1 is normally disconnected from the input and is only
connected to it at sampling time; 1.4pf
Equivalent input impedance, when the the input is selected =
5.
Figure 10-17 Equivalent Circuit for A/D Loading
10.16 Power Consumption
See
Section 10.1
for a list of IDD requirements for the 56F8014. This section provides additional detail
which can be used to optimize power consumption for a given application.
Power consumption is given by the following equation:
A, the internal [static component], is comprised of the DC bias currents for the oscillator, leakage currents,
PLL, and voltage references. These sources operate independently of processor state or operating
frequency.
B, the internal [state-dependent component], reflects the supply current required by certain on-chip
resources only when those resources are in use. These include RAM, Flash memory and the ADCs.
C, the internal [dynamic component], is classic C*V
2
*F CMOS power dissipation corresponding to the
56800E core and standard cell logic.
D, the external [dynamic component], reflects power dissipated on-chip as a result of capacitive loading
on the external pins of the chip. This is also commonly described as C*V
2
*F, although simulations on two
of the I/O cell types used on the 56800E reveal that the power-versus-load curve does have a non-zero
Y-intercept.
Total power =
A: internal [static component]
+B: internal [state-dependent component]
+C: internal [dynamic component]
+D: external [dynamic component]
+E: external [static]
1
2
3
Analog Input
4
S1
S2
S3
C1
C2
S/H
C1 = C2 = 1pF
(V
REFH
- V
REFL )
/ 2
125
ESD Resistor
8pF noise damping capacitor
1
(ADC Clock Rate) x 1.4 x 10
-12
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