參數(shù)資料
型號： MC56F8011VFAE
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號處理
英文描述： 0-BIT, 8 MHz, OTHER DSP, PQFP32
封裝： ROHS COMPLIANT, LQFP-32
文件頁數(shù)： 85/125頁
文件大?。?/td> 1702K
代理商： MC56F8011VFAE
56F8013/56F8011 Data Sheet, Rev. 11
62
Freescale Semiconductor
5.5.16
Interrupt Control Register (ICTRL)
Figure 5-18 Interrupt Control Register (ICTRL)
5.5.16.1
Interrupt (INT)—Bit 15
This read-only bit reflects the state of the interrupt to the 56800E core.
0 = No interrupt is being sent to the 56800E core
1 = An interrupt is being sent to the 56800E core
5.5.16.2
Interrupt Priority Level (IPIC)—Bits 14–13
These read-only bits reflect the state of the new interrupt priority level bits being presented to the 56800E
core. These bits indicate the priority level needed for a new IRQ to interrupt the current interrupt being
sent to the 56800E core. This field is only updated when the 56800E core jumps to a new interrupt service
routine.
Note:
Nested interrupts may cause this field to be updated before the original interrupt service routine can
read it.
00 = Required nested exception priority levels are 0, 1, 2, or 3
01 = Required nested exception priority levels are 1, 2, or 3
10 = Required nested exception priority levels are 2 or 3
11 = Required nested exception priority level is 3
5.5.16.3
Vector Number - Vector Address Bus (VAB)—Bits 12–6
This read-only field shows the vector number (VAB[6:0]) used at the time the last IRQ was taken. In the
case of a Fast Interrupt, it shows the lower address bits of the jump address. This field is only updated when
the 56800E core jumps to a new interrupt service routine.
$Base + $12
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
INT
IPIC
VAB
INT_
DIS
1
0
Write
RESET
00000
0000001
1100
Table 5-3 Interrupt Priority Encoding
IPIC_VALUE[1:0]
Current Interrupt
Priority Level
Required Nested
Exception Priority
00
No interrupt or SWILP
Priorities 0, 1, 2, 3
01
Priority 0
Priorities 1, 2, 3
10
Priority 1
Priorities 2, 3
11
Priority 2 or 3
Priority 3
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