- 您現在的位置：買賣IC網 > PDF目錄98011 > MC56F8011VFAE (FREESCALE SEMICONDUCTOR INC) 0-BIT, 8 MHz, OTHER DSP, PQFP32 PDF資料下載
參數資料
| 型號： | MC56F8011VFAE |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | 0-BIT, 8 MHz, OTHER DSP, PQFP32 |
| 封裝： | ROHS COMPLIANT, LQFP-32 |
| 文件頁數： | 110/125頁 |
| 文件大?。?/td> | 1702K |
| 代理商： | MC56F8011VFAE |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁當前第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁
Flash Security Enabling
56F8013/56F8011 Data Sheet, Rev. 11
Freescale Semiconductor
85
7.1 Flash Security Enabling
After the user has programmed the Flash with the application code, the 56F8013/56F8011 can be secured
by programming the security words located in the FM configuration field, which are located at the last nine
words of Program Flash. These non-volatile words will keep the part secured through reset and through
power-down of the device. To enable the flash security, program $E70A into program memory location
$1FF7. No other data programs in this location can secure the flash. Refer to the Flash Memory chapter in
the 56F801X Peripheral User Manual for more detail. When Flash security mode is enabled, the
56F8013/56F8011 will disable the core EOnCE debug capabilities. Normal program execution is
otherwise unaffected.
7.2 Flash Access Lock and Unlock Mechanisms
The 56F8013/56F8011 have several operating functional and debug modes. Effective Flash security must
address operating mode selection and anticipate modes in which the on-chip Flash can be read without
explicit user permission.
7.2.1
Disabling EOnCE Access
On-chip Flash can be read by issuing commands across the EOnCE port, which is the debug interface for
the 56800E CPU. The TCLK, TMS, TDO, and TDI pins comprise a JTAG interface onto which the
EOnCE port functionality is mapped. When the 56F8013/56F8011 boot, the chip-level JTAG TAP (Test
Access Port) is active and provides the chip’s boundary scan capability and access to the ID register, but
proper implementation of Flash security will block any attempt to access the internal Flash memory via
the EOnCE port when security is enabled.
7.2.2
Flash Lockout Recovery Using JTAG
If a user inadvertently enables security on the 56F8013/56F8011, the only lockout recovery mechanism is
the complete erasure of the internal Flash contents, including the configuration field, and thus disables
security (the protection register is cleared). This does not compromise security, as the entire contents of
the user’s secured code stored in Flash are erased before security is disabled on the 56F8013/56F8011 on
the next reset or power-up sequence.
To start the lockout recovery sequence, the JTAG public instruction (LOCKOUT_RECOVERY) must
first
be
shifted
into
the
chip-level
TAP
controller’s
instruction
register.
Once
the
LOCKOUT_RECOVERY instruction has been shifted into the instruction register, the clock divider value
must be shifted into the corresponding 7-bit data register. After the data register has been updated, the user
must transition the TAP controller into the RUN-TEST/IDLE state for the lockout sequence to commence.
The controller must remain in this state until the erase sequence has completed. Refer to the 56F801X
Peripheral User Manual for more details, or contact Freescale.
Note:
Once the lockout recovery sequence has completed, the user must reset both the JTAG TAP controller
(by advancing the TAP state machine to the reset state) and the 56F8013/56F8011 (by asserting
external chip reset) to return to normal unsecured operation.
相關PDF資料 |
PDF描述 |
|---|---|
| S568013MFA00E | 0-BIT, 8 MHz, OTHER DSP, PQFP32 |
| MC56F8023VLC | 16-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP32 |
| MC56F8033VLC | 16-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP32 |
| MC56F8347MPY60 | 16-BIT, 120 MHz, OTHER DSP, PQFP160 |
| MC56F8355VFG60 | 4-BIT, 120 MHz, OTHER DSP, PQFP128 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MC56F8013 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
| MC56F8013E | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
| MC56F8013MFAE | 功能描述:數字信號處理器和控制器 - DSP, DSC 16Bit DSPHC ANGUILLA RoHS:否 制造商:Microchip Technology 核心:dsPIC 數據總線寬度:16 bit 程序存儲器大小:16 KB 數據 RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數量:35 定時器數量:3 設備每秒兆指令數:50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
| MC56F8013MFAER2 | 制造商:Freescale Semiconductor 功能描述:16 BIT DSPHC ANGUILLA - Tape and Reel |
| MC56F8013PB | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
發(fā)布緊急采購，3分鐘左右您將得到回復。