
MB91460P Series
94
DS07-16615-2E
This flag is set after a write operation ended in timeout state.
This flag can generate an interrupt if DFWC:ERINTE is set.
This bit is cleared by software reset (RST) or by writing 0. Writing 1 has no effect.
Read-modify-write operations will read 1.
This flag is set after a command sequencer write operation was finished successfully.
This flag can generate an interrupt if DFWC:FININTE is set.
This bit is cleared by software reset (RST) or by writing 0. Writing 1 has no effect.
This bit is also cleared after a DMA transfer (caused by IDLINT) was finished.
Read-modify-write operations will read 1.
This flag is set after the command sequencer was enabled (set DFWC:WE=1) or entered the IDLE state after
a write operation was finished.
This flag can generate an interrupt if DFWC:INTE is set.
This flag can generate a DMA transfer request if DFWC:IDLDMAE is set.
This bit is cleared by software reset (RST) or by writing 0. Writing 1 has no effect.
This bit is also cleared after a DMA transfer was finished.
Read-modify-write operations will read 1.
Status bit {ST1,ST0} =2’b11 show that the command sequencer was disabled in "not idle" state and direct
access to Flash is not yet permitted (wait for proceeding Flash sequence to finish). Max duration of this wait
can be 11 clock cycle after disabling Command Sequencer.
5.4.
Data Flash security Control Register 0,1
FININT
Command Sequence Finished Flag
0
(default) Write command was not (yet) finished successfully
1
Write command was finished successfully
IDLINT
Command Sequencer Idle Flag
0
(default) Command sequencer is disabled or not in IDLE state
1
Command sequencer entered the IDLE state
ST1
ST0
Command Sequencer Status Flags
0
(default) Command sequencer is disabled or in IDLE state
0
1
Command sequencer is submitting the write command
1
0
Command sequencer is waiting for Flash program finish
1
Command sequencer was disabled in "not idle" state