
MB91460P Series
DS07-16615-2E
93
5.3.
Data Flash Write Command Sequencer Status Register
This section explaines the Data Flash Command Sequencer Status register.
DFWS : Data Flash Write Command Sequencer Status
The command sequencer status flags are only set if the command sequencer is enabled (DFWC:WE=1).
This flag is set if the CPU tried to read or write into the Data Flash area while the Data Flash is accessed by
the Command Sequencer.
This flag cannot generate an interrupt.
This bit is cleared by software reset (RST) or by writing 0. Writing 1 has no effect.
Read-modify-write operations will read 1.
This flag is set when the command sequencer is disabled (set DFWC:WE=0) in "not idle" state .
If this flag is 0, it is no guarantee that the write operation was successful. Use the FININT flag!
This flag can generate an interrupt if DFWC:ERINTE is set.
This bit is cleared by software reset (RST) or by writing 0. Writing 1 has no effect.
Read-modify-write operations will read 1.
This flag is set after a write access returned error:
- tried to write to an erase-suspended or write-protected sector,
- tried to write a bit “1” although it is already “0” in flash.
This flag can generate an interrupt if DFWC:ERINTE is set.
This bit is cleared by software reset (RST) or by writing 0. Writing 1 has no effect.
Read-modify-write operations will read 1.
Addr:
0x07116
15
14
13
12
11
10
9
8
bit
PAERF
WIERINT
WERINT
TOERINT
FININT
IDLINT
ST1
ST0
00000000
initial
R/W0
R
attribute
PAERF
Prohibited Access Error Flag
0
(default) No prohibited access detected
1
Prohibited access detected
WIERINT
Write Incomplete Error Flag
0
(default) Command sequencer write operation was completed
1
Command sequencer was disabled while a write operation was ongoing
WERINT
Write Error Flag
0
(default) No write error detected
1
Write operation returned error
TOERINT
Timeout Error Flag
0
(default) No timeout error detected
1
A write operation ended with timeout error