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參數(shù)資料
| 型號(hào)： | MB91F467PAPMC-GSE2 |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RISC MICROCONTROLLER, PQFP176 |
| 封裝： | 24 X 24 MM, 0.50 MM PITCH, LEAD FREE, PLASTIC, LQFP-176 |
| 文件頁數(shù)： | 184/200頁 |
| 文件大?。?/td> | 6566K |
| 代理商： | MB91F467PAPMC-GSE2 |
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MB91460P Series
84
DS07-16615-2E
3.
Data Flash Operation Modes
The data flash is located in the top address space of external bus area. Per default (after software reset RST),
the data flash is disabled and does not accept any read/write access. The data flash can be enabled by setting
the bit DFCS:FLASHEN (DFCS is the Data Flash Control/Status register).
3.1.
Direct Access mode:
The Direct Access mode provides data flash access similar to the access of the embedded program/data flash
(main flash). For write/program operations, the flash command sequences must be written by the CPU. The
command sequences are the same as used for the embedded program/data flash (main flash).
CPU reads data in byte, halfword or word (8/16/32-bit) length units, whereas 16- or 32-bit read operations are
split into 2 or 4 sequential 8-bit flash macro read accesses by hardware.
CPU writes data in byte (8-bit) width units.
For write/program operations, the flash command sequences must be written by the CPU.
The flash macro auto algorithms (Chip Erase, Sector Erase, Sector Erase Suspend,...) can only be activated
in direct access mode.
Direct access mode is the default mode after software reset (RST).
3.2.
Command Sequencer Mode:
In command sequencer mode, the flash macro command sequences for data write operation are generated by
hardware.
CPU reads data in byte, halfword or word (8/16/32-bit) length units (same as in direct access mode).
CPU writes data in byte, halfword or word (8/16/32-bit) length units using normal “store” instructions. The flash
macro command sequences are generated by internal command sequencer hardware. For 16- or 32-bit write,
2 or 4 command sequences are generated, respectively.
The data flash interface will not issue wait states after a command sequencer write operation was started. The
CPU can continue working during data flash programming.
If a command sequencer write operation is ongoing, and the CPU writes data again, this second write
request is ignored! The error flag DFWS:PAERF is set in case of such a prohibited access. It is recommended
to use the data flash interrupts, which indicate that the proceeding write sequence was finished and successful.
If a command sequencer write operation is ongoing, and the CPU tries to read data, 0x00 is returned
and the error flag DFWS:PAERF is set.
The flash macro auto algorithms (Chip Erase, Sector Erase, Sector Erase Suspend,...) cannot be activated.
Command Sequencer mode is enabled by setting the bit DFWC:WE (Data Flash Write Control register).
After software reset (RST), the command sequencer mode is disabled.
3.3.
Parallel Programming mode:
The parallel programming mode works similar to the main flash memory. The function/timing of some external
control lines are different.
In parallel programming mode, it is not necessary to set the Data Flash enable bit (DFCS:FLASHEN).
Data Flash Memory access is performed in byte (8-bit) length units.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB91F469GBPB-GS | 32-BIT, FLASH, 88 MHz, RISC MICROCONTROLLER, PBGA320 |
| MB91F469GAPB-GS | 32-BIT, FLASH, 88 MHz, RISC MICROCONTROLLER, PBGA320 |
| MB91F469QAPB-GSE1 | RISC MICROCONTROLLER, PBGA320 |
| MB91F469TAPMC-GSE2 | 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP144 |
| MB91F467TAPMC-GSE2 | 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP144 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB91F467R | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit Microcontroller |
| MB91F467RCPMC-GE1 | 制造商:FUJITSU 功能描述: |
| MB91F467RCPMC-GSE1 | 制造商:FUJITSU 功能描述: |
| MB91F467RDPMC-ESE2 | 制造商:FUJITSU 功能描述: |
| MB91F467RDPMC-GSE2 | 制造商:FUJITSU 功能描述: |
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