參數(shù)資料
型號: MB90F897SPMT
元件分類: 微控制器/微處理器
英文描述: MICROCONTROLLER, PQFP48
封裝: 7 X 7 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-48
文件頁數(shù): 39/84頁
文件大?。?/td> 1773K
代理商: MB90F897SPMT
MB90895 Series
44
DS07-13731-4E
9.
DTP/External Interrupt and CAN Wakeup Outline
DTP/external interrupt transfers an interrupt request generated by an external peripheral device or a data trans-
mission request to CPU, generating external interrupt request and activating expanded intelligent I/O service.
Input RX of CAN controller is used as external interrupt input.
DTP/external interrupt and CAN wakeup function
An interrupt request input from external peripheral device to external input pins (INT7 to INT4) and RX pin, just
as interrupt request of peripheral device, generates an interrupt request. The interrupt request generates an
external interrupt and activates expanded intelligent I/O service (EI2OS).
If the expanded intelligent I/O service (EI2OS) has been disabled by interrupt control register (ICR : ISE=0),
external interrupt function is enabled and branches to interrupt processing.
If the EI2OS has been enabled, (ICR : ISE=1), DTP function is enabled and automatic data transmission is
performed by EI2OS. After performing specified number of data transmission processes, the process branches
to interrupt processing.
DTP/external interrupt and CAN wakeup outline
External interrupt
DTP function
Input pin
5 pins (RX, and INT4 to INT7)
Interrupt cause
Specify for each pin with detection level setting register (ELVR).
Input of “H” level/“L” level/rising edge/falling
edge.
Input of “H” level/ “L” level
Interrupt number
#15 (0FH) , #24 (18H) , #27 (1BH)
Interrupt control
Enabling or disabling output of interrupt request, using DTP/external interrupt permission
register (ENIR).
Interrupt flag
Retaining interrupt cause with DTP/external interrupt cause register (EIRR).
Process selection
Disable EI2OS (ICR : ISE=0)
Enable EI2OS (ICR : ISE=1)
Process
Branch to external interrupt process
After automatic data transmission by EI2OS for
specified number of times, branch to interrupt
process.
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