- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45192 > MB90F897SPMT MICROCONTROLLER, PQFP48 PDF資料下載
參數(shù)資料
| 型號(hào)： | MB90F897SPMT |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROCONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-48 |
| 文件頁(yè)數(shù)： | 25/84頁(yè) |
| 文件大?。?/td> | 1773K |
| 代理商： | MB90F897SPMT |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)當(dāng)前第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)
MB90895 Series
DS07-13731-4E
31
3.
Watchdog Timer
The watchdog timer is a 2-bit counter that uses time-base timer or watch timer as count clock. If the counter is
not cleared within an interval time, CPU is reset.
Watchdog timer functions
The watchdog timer is a timer counter that prevents runaway of a program. Once a watchdog timer is activated,
the counter of watchdog timer must always be cleared within a specified time of interval. If specified interval
time elapses without clearing the counter of a watchdog timer, CPU resetting occurs. This is the function of a
watchdog timer.
The interval time of a watchdog timer is determined by a clock cycle, which is input as a count clock. Watchdog
resetting occurs between a minimum time and a maximum time specified.
The output target of a clock source is specified by the watchdog clock selection bit (WTC: WDCS) in the watch
timer control register.
Interval time of a watchdog timer is specified by the time-base timer output selection bit/watch timer output
selection bit (WDTC: WT1, WT0) in the watchdog timer control register.
Interval timer of watchdog timer
HCLK: Oscillation clock ( 4 MHz) , CSCLK: Sub clock (8.192 kHz)
Notes:
If the time-base timer is cleared when watchdog timer count clock is used as time base timer output
(carry-over signal), watchdog reset time may become longer.
When using the sub clock as machine clock, be sure to specify watchdog timer clock source selection bit
(WDCS) in watch timer control register (WTC) at “0,” selecting output of watch timer.
Min
Max
Clock cycle
Min
Max
Clock cycle
Approx. 3.58 ms
Approx. 4.61 ms
214
±211
/HCLK
Approx. 0.457 s Approx. 0.576 s
212
±29
/SCLK
Approx. 14.33 ms Approx. 18.3 ms
216
±213
/HCLK
Approx. 3.584 s Approx. 4.608 s
215
±212
/SCLK
Approx. 57.23 ms Approx. 73.73 ms
218
±215
/HCLK
Approx. 7.168 s Approx. 9.216 s
216
±213
/SCLK
Approx.
458.75 ms
Approx.
589.82 ms
221
±218
/HCLK
Approx.
14.336 s
Approx.
18.432 s
217
±214
/SCLK
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB90F922NB | 16-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP120 |
| MB90F923NA | 16-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP120 |
| MB90F923NAS | 16-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP120 |
| MB90F924NAS | 16-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP120 |
| MB90F952MBSPFV | 16-BIT, FLASH, 32 MHz, MICROCONTROLLER, PQFP100 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB90F947APFR-GS-SPE1 | 制造商:FUJITSU 功能描述: |
| MB90F962SPMCR-GE1 | 制造商:FUJITSU 功能描述:IC MCU 16BIT 16LX 48LQFP |
| MB90F962SPMCR-G-JNE1 | 制造商:FUJITSU 功能描述: |
| MB90V340A-102CR | 制造商:FUJITSU 功能描述: |
| MB-910 | 制造商:Circuit Test 功能描述:BREADBOARD WIRING KIT - 350 PCS |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。