參數(shù)資料
型號: MB89951PFM
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 5 MHz, MICROCONTROLLER, PQFP64
封裝: 0.65 MM PITCH, QFP-64
文件頁數(shù): 96/110頁
文件大?。?/td> 619K
代理商: MB89951PFM
HARDWARE CONFIGURATION
2– 71
2.2.9 Watchdog Timer Reset
A watchdog reset is generated using the output of the time-based timer as
a clock pulse.
(1) Block diagram
(2) Registers
The watchdog timer reset has one watchdog timer control register (WDTE).
(3) Description of register
The detail of the watchdog timer control register (WDTE) is described below.
[Bits 3 to 0] WTE3 to WTE0: Watchdog timer control bits
These bits are used to control the watchdog timer.
First write only after reset
Second and later write
The watchdog timer can be stopped only by reset. These bits are read 1111.
Peripherals
WTE3 to WTE0
2-bit counter
RST
Reset control
Time-base timer
CLR
Start
OF
Address: 0009H
WDTE
8 bits
R/W Watchdog timer control register
(a) Watchdog timer control register (WDTE)
WDTE
Address: 0009H
Address: 0009H
(Initial value)
XXXXXXXXB
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
————
WTE3
WTE2
WTE1
WTE0
(W)
Starts watchdog timer
No operation
0101
Other than the above
Clears watchdog timer counter
No operation
0101
Other than the above
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