參數(shù)資料
型號(hào): MB89951PFM
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 5 MHz, MICROCONTROLLER, PQFP64
封裝: 0.65 MM PITCH, QFP-64
文件頁(yè)數(shù): 26/110頁(yè)
文件大?。?/td> 619K
代理商: MB89951PFM
HARDWARE CONFIGURATION
2– 7
The 16 bits of the processor status (PS) can be divided into 8 upper bits
for a register bank pointer (RP) and 8 lower bits for a condition code register
(CCR). (See Fig. 2.4.)
Fig. 2.4 Structure of Processor Status
The RP indicates the address of the current register bank. The relationship
between the contents of the RP and the real addresses is as shown in
Figure 2.5.
Fig. 2.5 Rule for Translating Real Addresses at General-purpose Register Area
The CCR has bits indicating the results of operations and transfer data
contents, and bits controlling the CPU operation when an interrupt occurs.
- H-flag
H-flag is set when a carry or a borrow out of bit 3 into bit 4
is generated as a result of operations; it is cleared in other
cases. This flag is used for decimal-correction instructions.
- I-flag
An interrupt is enabled when this flag is 1 and is disabled
when it is 0. The I-flag is 0 at reset.
- IL1 and IL0 These bits indicate the level of the currently-enabled
interrupt. The CPU executes interrupt processing only when
an interrupt with a value smaller than the value indicated by
this bit is requested.
- N-flag
The N-flag is set when the most significant bit is 1 as a result
of operations; it is cleared when the MSB is 0.
IL1
IL0
Interrupt level
High and low
00
1
High
low = No interrupt
01
10
2
11
3
CPU
PS
15
14
13
12
11
10
987
6543210
RP
Vacant Vacant Vacant
HI
N
Z
V
C
RP
CCR
IL1, 0
R P
A15 A14 A13 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
‘0’
‘1’
R4
R3
R2
R1
R0
b2
b1
b0
↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓↓
Source address
Lower bits of OP code
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