參數(shù)資料
型號(hào)： MB89951PFM
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 5 MHz, MICROCONTROLLER, PQFP64
封裝： 0.65 MM PITCH, QFP-64
文件頁(yè)數(shù)： 95/110頁(yè)
文件大小： 619K
代理商： MB89951PFM
HARDWARE CONFIGURATION
2– 70
(3) Description of registers
The detail of time-base timer control register (TBCR) is described below.
[Bit 4] TBIE: Interval-timer interrupt enable bit
This bit is used to enable an interrupt by the interval timer.
[Bit 3] TBIF: Interval timer overflow bit
When writing, this bit is used to clear the interval timer overflow flag.
When reading, this bit indicates that an interval timer overflow has occurred.
During Read Modify Write instruction, 1 is always read. If the TBIF bit is
set to 1 when the TBIE bit is 1, an interrupt request is output. This bit is
cleared upon reset.
[Bit 2] TBR: Time-base timer clear bit
This bit is used to clear time-base timer.
This bit is always read 1.
[Bits 1 and 0] TBC1, TBC0: Interval time specification bits
These bits are used to specify interval timer cycle
.
Peripherals
(a) Time-base timer control register (TBCR)
TBCR
Address: 000AH
Address: 000AH
(Initial value)
XXX00000B
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
TBIE
TBIF
TBR
TBC1
TBC0
(R/W)
(W)
(R/W)
Disables interval interrupt
Enables interval interrupt
0
1
Clears interval timer overflow flag
No operation
0
1
No interval timer overflow
Interval timer overflow
0
1
Clears time-base timer
No operation
0
1
6.55 [ms]
26.21 [ms]
104.86 [ms]
0.42 [s]
0
1
0
1
0
1
215/fCH
217/fCH
219/fCH
221/fCH
TBC1
TBC0
Interval time
fCH: clock frequency
Value at fCH = 5 MHz
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