參數(shù)資料
型號(hào): MB89951PFM
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 5 MHz, MICROCONTROLLER, PQFP64
封裝: 0.65 MM PITCH, QFP-64
文件頁數(shù): 35/110頁
文件大?。?/td> 619K
代理商: MB89951PFM
HARDWARE CONFIGURATION
2– 15
2.1.5 Interrupt Controller
The interrupt controller for the F2MC-8L family is located between the CPU
and each peripheral. This controller receives interrupt requests from the
peripherals, assigns priority to them. When the interrupt controller transfers
the priority to the CPU, it also decides the priority of same-level interrupts.
(1) Block diagram
(2) Register list
Interrupt controller consists of interrupt-level registers (ILR1, 2, and 3) and
interrupt-test register (ITR).
CPU
Level
Peripheral #1
Peripheral #2
Peripheral #n
CPU
F2MC-8L bus
Test
register
Address decoder
G
L
Level
deciding
block
G
L
G
Same level
priority
deciding
block
Interrupt
vector
generation
block
2
Address: 007CH
Address: 007DH
Address: 007EH
Address: 007FH
ILR1
ILR2
ILR3
ITR
8 bits
W
Interrupt level register #1
W
Interrupt level register #2
W
Interrupt level register #3
Interrupt test register
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